Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Post
Hot topic Haswell GFLOPS (Page: 1, 2)
by caosun
Wed, 06/26/2013 - 02:42 72
by Abhishek J.
Thu, 08/18/2016 - 01:06
Normal topic PIN Failure to initialize DLL file python27.dll
by Albert g.
Mon, 01/25/2016 - 14:58 3
by Ben C.
Thu, 08/04/2016 - 22:36
Normal topic monitor/mwait disabled by IA32_MISC_ENABLES MSR?
by godofpumpkins
Fri, 02/13/2009 - 19:11 3
by Igor Levicki
Sat, 02/14/2009 - 11:02
Normal topic Cycle counts of the new Westmere instructions
by Cryptographer
Tue, 04/13/2010 - 00:10 2
by neni
Tue, 04/13/2010 - 00:10
Normal topic avx instruction choice
by zhangxiuxia
Mon, 02/20/2012 - 04:55 9
by Max Locktyukhin...
Wed, 02/22/2012 - 18:41
Normal topic ippGetCpuFeatures for AVX2 support
by bronxzv
Sun, 03/09/2014 - 09:47 9
by bronxzv
Wed, 03/12/2014 - 16:19
Normal topic Retrieving/querying Intrinsic Guide
by Rashawn K. (Intel)
Thu, 10/27/2016 - 08:26 6
by jimdempseyatthecove
Sat, 11/05/2016 - 05:59
Normal topic quad core q9550 question
by threetwo
Wed, 07/08/2009 - 09:47 0
by threetwo
Wed, 07/08/2009 - 09:47
Normal topic adding a constant to array addition in sse2
by Smart Lubobya
Sun, 07/25/2010 - 07:19 1
by Brijender Bhart...
Tue, 07/27/2010 - 11:13
Normal topic Intel Graphics Driver Error
by Surya K.
Wed, 09/26/2012 - 16:19 0
by Surya K.
Wed, 09/26/2012 - 16:19
Normal topic Benefits of SSE/AVX processing when an integrated GPU is missing?
by Toby
Tue, 12/16/2014 - 07:08 5
by Toby
Tue, 12/16/2014 - 09:35
Normal topic List of interrupss
by Joseph R.
Sun, 04/23/2017 - 09:36 2
by Sergey Kostrov
Tue, 04/25/2017 - 09:39
Normal topic TSC Problem
by faball
Fri, 11/27/2009 - 02:52 0
by faball
Mon, 01/11/2010 - 09:36
Normal topic _byteswap_ulong
by ms2579
Wed, 10/20/2010 - 09:47 1
by Nicolae Popovic...
Wed, 10/20/2010 - 09:47
Normal topic SSE sum of vectors - how to improve cache performance
by Daniel B.
Thu, 02/28/2013 - 23:26 2
by Daniel B.
Fri, 03/15/2013 - 05:21
Normal topic No explanation of comparison codes for integer vector compare instructions
by Michael R.
Wed, 07/29/2015 - 14:42 3
by jimdempseyatthecove
Wed, 08/05/2015 - 04:19
Normal topic AVX512-VBMI2: VPSHLDV masks its shift count preventing use as a blend
by Peter Cordes
Sat, 12/09/2017 - 12:23 0
by Peter Cordes
Sat, 12/09/2017 - 12:23
Hot topic Converging AVX and LRBni (Page: 1, 2)
by c0d1f1ed
Tue, 05/10/2011 - 23:27 62
by c0d1f1ed
Fri, 07/01/2011 - 03:59
Normal topic SSE3 critique
by Deleted User
Fri, 08/19/2005 - 08:35 3
by Igor Levicki
Tue, 05/27/2008 - 09:59
Normal topic Proposal: Extended setcc
by sirrida
Wed, 05/11/2011 - 15:42 2
by sirrida
Thu, 05/12/2011 - 07:51
Normal topic Array of _m128d values as function argument
by n.anastop
Tue, 03/19/2013 - 06:43 8
by iliyapolak
Fri, 03/22/2013 - 05:42
Normal topic BMI support in Skylake
by bronxzv
Tue, 08/18/2015 - 01:41 11
by jimdempseyatthecove
Fri, 08/28/2015 - 08:15
Normal topic AVX-512 VBMI2: why no vector version of _pext_u32()?
by Mikkelsen, Morten
Thu, 01/11/2018 - 16:24 0
by Mikkelsen, Morten
Thu, 01/11/2018 - 16:24
Hot topic How many MMX/SSE units in Core-2 Quad
by murzik
Mon, 08/25/2008 - 09:03 31
by iliyapolak
Mon, 03/30/2015 - 23:25
Normal topic Illegal Instruction -- Intel SDE with AES instructions
by rksm
Tue, 12/01/2009 - 07:58 3
by Mark Charney (Intel)
Tue, 12/01/2009 - 07:58
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For more complete information about compiler optimizations, see our Optimization Notice.