Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX, a security technology designed for developers wanting to protect select application code and data from disclosure or modification
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic movd instruction not working with Masm 8.0
by slider77
Wed, 07/22/2009 - 14:04 1
by mazegen
Wed, 07/22/2009 - 14:04
Normal topic SFENCE and peripheral devices
by dm7
Mon, 10/15/2007 - 01:21 1
by Intel Software ...
Tue, 10/16/2007 - 08:36
Normal topic small typo in Intel® 64 and IA-32 Architectures Software Developer’s Manual
by Bea T.
Tue, 06/30/2015 - 02:31 1
by Mark Charney (Intel)
Tue, 06/30/2015 - 05:22
Normal topic What does it implies to disable syscall in Intel SGX
by Fan Z.
Tue, 01/27/2015 - 19:07 1
by Shih Kuo (Intel)
Sat, 03/28/2015 - 06:46
Normal topic Use AVX; fallback to SSE4.2
by Levi Morrison
Wed, 11/07/2012 - 11:05 1
by Tim P.
Wed, 11/07/2012 - 18:09
Normal topic vertical sync
by dido88
Wed, 06/01/2011 - 11:39 1
by Thomas Willhalm...
Wed, 06/01/2011 - 11:39
Normal topic Is profiling information running on SDE accurate and trustable?
by WEI Z. (Intel)
Sun, 03/01/2015 - 04:50 1
by Mark Charney (Intel)
Sun, 03/01/2015 - 04:55
Normal topic Timing of LPT-port
by ugtehservis
Wed, 09/03/2008 - 23:36 1
by Igor Levicki
Tue, 09/30/2008 - 17:35
Normal topic Intel SGX SDK under Windows 10 threshold 2
by sungjin p.
Thu, 01/21/2016 - 18:57 1
by Simon Johnson (...
Fri, 01/22/2016 - 15:37
Normal topic Instructions Retired Equation
by gokussj9
Fri, 10/01/2010 - 12:38 1
by Thomas Willhalm...
Mon, 10/04/2010 - 01:55
Normal topic Intel processor data sheets
by logicman112
Tue, 08/03/2010 - 01:44 1
by Aubrey W. (Intel)
Tue, 08/03/2010 - 01:44
Normal topic Is there an error in Operation pseudo-code for FSIN instruction?
by Sergey Kostrov
Mon, 07/23/2012 - 16:20 1
by iliyapolak
Mon, 07/23/2012 - 17:07
Normal topic A Question about MSR ?
by zp s.
Tue, 04/07/2015 - 10:16 1
by John McCalpin
Tue, 04/07/2015 - 13:26
Normal topic AMX Analysis - GNU & Intel
by srimks
Sat, 11/08/2008 - 06:14 1
by Tim P.
Wed, 11/12/2008 - 23:12
Normal topic _byteswap_ulong
by ms2579
Wed, 10/20/2010 - 09:47 1
by Nicolae Popovic...
Wed, 10/20/2010 - 09:47
Normal topic Intel TSX-NI with m3-6Y30 processor
by Jeremy W.
Wed, 01/06/2016 - 07:48 1
by Mark Charney (Intel)
Tue, 01/12/2016 - 14:13
Normal topic instructional change __m128i
by lex
Sat, 06/14/2014 - 14:28 1
by Thomas Willhalm...
Sun, 06/15/2014 - 14:55
Normal topic Intel manual has some mistakes
by logicman112
Sat, 06/26/2010 - 21:01 1
by logicman112
Sat, 06/26/2010 - 21:01
Normal topic A problem of iret instruction description in Intel 64 and IA-32 Architectures Software Developers Manual
by Jingguo Yao
Wed, 04/25/2012 - 23:41 1
by Shih Kuo (Intel)
Fri, 04/27/2012 - 14:54
Normal topic SGX EGETKEY clarification?
by Patrick B.
Thu, 06/11/2015 - 09:52 1
by Simon Johnson (...
Mon, 08/17/2015 - 11:12
Normal topic CPU Instruction counter register
by nuclear_scientist
Fri, 07/31/2009 - 09:37 1
by Tim P.
Fri, 07/31/2009 - 09:37
Normal topic psubw code gave wrong result
by Smart Lubobya
Tue, 07/13/2010 - 04:47 1
by neni
Tue, 07/13/2010 - 04:47
Normal topic How to disable FPU on Intel Core2 Duo
by adamczez
Sat, 05/02/2009 - 03:26 1
by jancino
Sat, 05/02/2009 - 03:26
Normal topic Binary operators a%b and a/b in SSE2
by Smart Lubobya
Fri, 07/23/2010 - 08:13 1
by neni
Fri, 07/23/2010 - 08:13
Normal topic Penalty for 256-bit loads and stores with cache line splits
by jeremyweek
Tue, 05/10/2011 - 08:03 1
by Tim P.
Tue, 05/10/2011 - 08:03
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For more complete information about compiler optimizations, see our Optimization Notice.