Intel® Developer Zone:
Intel ISA Extensions

Announcements
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic Blog post about various routes to AVX vectorisation
by walkingrandomly
Sat, 08/25/2012 - 11:58 0
by walkingrandomly
Sat, 08/25/2012 - 11:58
Normal topic Does LBR_SELECT apply to BTF?
by tarmeneldur
Fri, 04/02/2010 - 11:20 2
by tarmeneldur
Fri, 04/02/2010 - 11:24
Normal topic Does the cache prefetcher will abort the rtm transaction?
by zhaoguo w.
Sat, 06/22/2013 - 06:56 5
by John McCalpin
Mon, 06/24/2013 - 15:46
Normal topic 4K False Store Forwarding...
by Evren Yurtesen
Tue, 10/19/2010 - 05:29 1
by Thomas Willhalm...
Tue, 10/19/2010 - 05:29
Normal topic Huge time cost while assigning
by Xinjue Z.
Wed, 12/03/2014 - 18:12 10
by jimdempseyatthecove
Wed, 12/10/2014 - 05:57
Normal topic Diagnostic testing of CPU and Support Device Architectures
by daryl_langley_4
Mon, 12/01/2008 - 17:06 1
by Thai Le (Intel)
Tue, 12/09/2008 - 13:51
Normal topic float precise
by zhangxiuxia
Wed, 04/18/2012 - 20:33 5
by Sergey Kostrov
Tue, 04/24/2012 - 18:19
Normal topic gmmintrin.h / AVX intrinsics
by rksm
Thu, 09/24/2009 - 04:27 1
by bronxzv
Fri, 09/25/2009 - 08:30
Normal topic __m128 vs __m128i
by ivantsou
Wed, 08/11/2010 - 13:33 1
by Brijender Bhart...
Wed, 08/11/2010 - 14:34
Normal topic SDE emulation issue
by srinivasu
Thu, 06/05/2014 - 00:30 4
by Mark Charney (Intel)
Mon, 06/09/2014 - 13:21
Hot topic sse execution units in core duo
by s.gautam
Wed, 06/18/2008 - 04:23 23
by maa1
Wed, 06/18/2008 - 04:23
Normal topic SHA Extensions are availabe on which microarchitecture?
by Andreas T.
Tue, 06/14/2016 - 15:00 1
by andysem
Wed, 06/29/2016 - 04:59
Normal topic Getting started
by Guy M.
Mon, 12/19/2011 - 16:00 0
by Guy M.
Mon, 12/19/2011 - 16:00
Normal topic Help an Assembler Noob, it's good karma
by tyrch
Tue, 07/07/2009 - 16:06 6
by Agner
Tue, 07/07/2009 - 16:06
Normal topic VEX encoding - 32bit and 64bit
by Christian M.
Fri, 01/18/2013 - 04:05 2
by Christian M.
Sat, 01/19/2013 - 01:40
Normal topic x64 Intrinsic Reference
by inteleverywhere
Wed, 06/23/2010 - 22:43 3
by matthieu.darbois
Wed, 06/23/2010 - 22:43
Normal topic mem address directly from SSE/AVX register
by Luchezar B.
Thu, 11/14/2013 - 04:02 3
by John McCalpin
Thu, 11/14/2013 - 10:44
Normal topic Message Address Register: Redirection hint & Destination mode
by Yunju K.
Mon, 01/18/2016 - 02:58 1
by Yunju K.
Wed, 01/20/2016 - 16:14
Normal topic Looking for efficient way to convert float (32 bit) aligned buffer to short (16 bit) aligned buffer
by gilgil
Tue, 07/05/2011 - 05:26 1
by Matthias Kretz
Tue, 07/05/2011 - 06:56
Normal topic Signed Saturation of integers
by Prashanthns
Fri, 02/11/2011 - 04:39 1
by Max Locktyukhin...
Tue, 03/08/2011 - 08:25
Normal topic Cache and _mm_prefetch
by Christian M.
Sun, 05/10/2015 - 04:10 5
by Vladimir Sedach
Wed, 05/13/2015 - 02:45
Normal topic about partial register stalls
by hurricanezhb
Sat, 04/04/2009 - 00:45 3
by srimks
Sat, 04/04/2009 - 00:45
Normal topic Will AVX-512 replace the need for dedicated GPU's?
by Christopher H.
Mon, 01/13/2014 - 01:44 13
by iliyapolak
Fri, 01/24/2014 - 12:28
Normal topic RDTSC variability in Core 2 Quad
by agame
Fri, 02/08/2008 - 19:31 1
by Tim P.
Sat, 02/09/2008 - 06:21
Normal topic Highest valid sub-leaf index of CPUID(EAX = 0DH)
by Jeremy W.
Fri, 02/05/2016 - 11:09 2
by Jeremy W.
Fri, 02/05/2016 - 11:49
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.