Any details about the physical address and cache line mappings?

Any details about the physical address and cache line mappings?

Some of the Xeon Phi documentation mentions that physical addresses are distributed among the memory controllers using a hashing function, and that cache line tags are distributed among the per-core portions of the distributed tag directory via a (presumably different) hashing function.

I'd like to know the details of those hashing functions.  I'm trying to measure what the latencies and bandwidths are for memory accesses as a function of the originating core and the targeted memory controller (and likewise for local L2 misses as a function of (a) originating core, (b) which core hosts the tag directory portion, and (c) which core holds the data in its L2).

I realise this is extremely low-level and perhaps beyond what Intel wants to document, but it's something we need to know for our performance tools.

Or are all communication costs perfectly symmetrical?

/Mikael

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Hi Mikael,

I missed your post due to the holidays.

I'll see what I can find out.

Regards
--
Taylor

Hi Mikael,

The text below was meant for another thread.

The low-level engineers consider the information too sensative for many reasons to release in this public forum.

I believe your company has an NDA relationship with Intel. You might have more success pursuing this topic through that connection.

Regards
---
Taylor

<text-deleted>

The good news: It took some effort to find it, but there will be some information forthcoming and it's positive.

The bad news: The authors prefer to publish the data in a more formal piece of collateral. This means sometime in the next couple of months.

Regards
--
Taylor

</text-deleted>

 

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