I notice that Xeon Phi has large coherent L2 cache. I'd like to figure out more details. My question is about where to apply the replacement policy.
Suppose thread0 in core0, want to read a data, suppose the data is neither in the local L2 or in other cores' L2, then it will access the main memory and bring the data to the L2 cache. My question is, if the local L2 is full, Xeon Phi will apply the cache replacement policy to the local L2, or possibly to other core's L2? (for example, if other cores' L2 is not full, then it can directly use that L2 cache lines?)
I cannot figure out this detail from documents, help you guys can help, thanks very much