raw latency

raw latency


In the SDG of Xeon Phi, it says the access time of L1 and L2 cache in terms of 'raw latency'. It is 1 cycle for the L1 cache and 11 cycles for the L2 cache. I wonder what does the 'raw latency' mean? And what's the difference from the 'real latency' seen by us programmers? 


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I don't know what Intel means by "raw latency" for L2 accesses, but I have measured L2 cache hit latency at about 25 cycles using a couple of different techniques. 

"Dr. Bandwidth"

The commonly accepted meaning of raw latency is the ideal latency for accessing the data in a single cache line. Real measurements often include other factors that will add to the ideal latency. 

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