I have a legacy code that utilizes threads and SSE instructions heavily. I wanted to port the code to the MIC cores, and could not succeed obviously because Intel® Xeon Phi™ cores do not support Intel Advanced Vector Extensions (Intel® AVX), or any of the Intel® Streaming SIMD Extensions (Intel® SSE) for some reason.
What is the easiest way to port my vector instructions to MIC so that I could still continue using vector instructions manually? The first obvious solution is to use the native SIMD of MIC cores, VPU and those zmm registers. Go over the SSE/SSE2 instructions one by one and convert them all, quite a headache.
Any other solutions, workarounds for porting SSE instructions to MIC cores?
Why did Intel drop SSE or AVX in Phi coprocessors and introduced a new set of zmm registers instead of old ones? That causes lots of problems for the codes that rely on manual SIMD optimization (using SSE/AVX) to be able to run on Xeon Phi...
Thanks in advance.