Quad precision architecture one day?

Quad precision architecture one day?


I have a dream in which the IEEE-754 quad precision is implemented in hardware in order to allow fast extended precision computation in a portable way instead of the current 80-bit extended format. I would like to know whether this is just a dream for the next 20 years or whether there are current research in this direction because there is a clear need of this for the HPC/physicists community.

Thank you in advance...

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The general consensus in the last 30 years has been that there is not enough demand for fast quad-precision (Binary128) to justify a hardware implementation. I am not aware of any research that could make this policy change in the near future.

Some IBM CPUs do support quad-precision decimal floating-point (Decimal128) in hardware. But they implement it with scalar, non-pipelined units that are orders of magnitude slower than double-precision (Binary64) SIMD units: their target is financial applications, not HPC.

When you mention there is a clear need for quad precision (or extended precision), do you have specific applications in mind? Have you considered software alternatives such as double-double arithmetic?

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