I am curious to know how is page tables are implemented in MIC as well as on Xeon architecture or these are completely OS depend.
Is there a single page table which is accessed by all the cores or each core has a part of page table .
The Intel document "Intel Xeon Phi Coprocessor System Software Developers Guide" (document 328207-002EN, June 2013) has a brief description of the page tables (pages 21-22). It seems clear from the description that the hardware is very similar to that of other Intel processors, but with a few restrictions. The processor supports the standard 4-level hierarchical page tables, which means that each process has its own set of page tables (starting at the address pointed to by the CR3 register). So if you run an OpenMP program that uses all the cores, they will all be using a single set of page tables. On the other hand if you run independent processes on each core, the processes (and therefore the processors) will each be accessing independent page table hierarchies.
Most recent Intel processors support "Global" page table entries, which can be accessed by any process. These are not supported on Xeon Phi.