Intel® Developer Zone:
Intel® Many Integrated Core Architecture (Intel MIC Architecture)

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Intel® Xeon Phi™

Intel® Xeon Phi™ Coprocessor is the brand name for all Intel® Many Integrated Core Architecture (Intel MIC Architecture) based products. At the end of 2012, Intel launched the first generation of the Intel Xeon Phi product family (coprocessors codenamed "Knights Corner") complementing the existing Intel® Xeon® processor product families to deliver new levels of performance for highly parallel workloads.

This forum is for discussion of public information about Intel MIC Architecture, Intel Xeon Phi Coprocessors, and preparing code to fully utilize this class of machines whether on a single chip or not (this is the key to programming the coprocessor).

Please visit the Developer zone at http://software.intel.com/mic-developer to see all documentation resources available for assessing, configuring, programming, and optimizing for Intel Xeon Phi Coprocessors.

Questions will be answered by both peers and Intel representatives that monitor this forum.

We invite you to subscribe to this forum to see new threads and updates (see button below, on the right). Please also note the ability to search for specific information within this forum, by clicking the button below, on the left.

Topic / Topic starter Post datesort descending Replies Last Post
Normal topic What's the highest performance Sandybridge CPU available in China?
by haixiao j.
Mon, 10/15/2012 - 07:28 1
by Tim Prince
Fri, 10/19/2012 - 09:24
Normal topic Simple question about (Xeon Phi) card extension
by bustaf
Fri, 10/19/2012 - 08:26 14
by bustaf
Tue, 02/12/2013 - 09:27
Normal topic how to request a Xeon Phi development kit
by gormot
Mon, 10/22/2012 - 09:25 3
by Tim Prince
Tue, 11/20/2012 - 07:10
Normal topic Re: Access to Technology Raodmaps
by Ted R.
Sun, 10/28/2012 - 12:18 1
by Ronald W Green ...
Fri, 11/02/2012 - 13:01
Normal topic Xeon E5 L3 cache is organized how?
This topic has been moved to "Software Tuning, Performance Optimization & Platform Monitoring" (View topic)
Normal topic MPSS Installation micflash
by Aurelio Rodrfguez
Fri, 11/09/2012 - 01:58 10
by Aurelio Rodrfguez
Mon, 01/07/2013 - 00:48
Normal topic Windows
by Petros Mamales
Tue, 11/13/2012 - 14:53 7
by BELINDA L. (Intel)
Mon, 05/06/2013 - 18:42
Normal topic How to use MIC Intrinsics?
by Harnz
Wed, 11/14/2012 - 03:23 5
by Kevin Davis (Intel)
Tue, 12/04/2012 - 04:54
Normal topic How to use swizzling ?
by Erik Saule
Thu, 11/15/2012 - 09:19 3
by Erik Saule
Tue, 11/20/2012 - 07:18
Normal topic Tranining program for MIC
by Dilum B.
Thu, 11/15/2012 - 18:29 4
by Dilum B.
Mon, 11/26/2012 - 15:51
Normal topic OMP_WAIT_POLICY
by Diego Caballero
Fri, 11/16/2012 - 10:52 4
by Andrey Churbano...
Wed, 12/12/2012 - 11:19
Normal topic Minimal requirements
by Petros Mamales
Wed, 11/21/2012 - 08:00 5
by Petros Mamales
Wed, 11/21/2012 - 17:33
Normal topic Kernel Trace and/or Debug Tools ?
by Wendy C.
Mon, 12/03/2012 - 12:50 5
by Wendy C.
Wed, 12/12/2012 - 09:55
Normal topic Assemblers for the new instructionset
by Paul C.
Tue, 12/04/2012 - 03:33 7
by Kevin Davis (Intel)
Tue, 12/04/2012 - 08:48
Normal topic how to deal with structure of arrays in the pragma offload model
by King Crimson
Tue, 12/04/2012 - 22:57 3
by King Crimson
Thu, 12/06/2012 - 20:56
Normal topic two questions, timing and memory
by King Crimson
Fri, 12/07/2012 - 18:30 2
by Charles Congdon...
Fri, 01/04/2013 - 12:57
Normal topic Two questions about Intel Xeon Phi Coprocessor before deciding to buy one
by Tommy Y.T. HU
Sun, 12/09/2012 - 01:47 9
by Tommy Y.T. HU
Tue, 06/11/2013 - 18:47
Normal topic Affinity
by ale
Mon, 12/10/2012 - 16:48 1
by Tim Prince
Mon, 12/10/2012 - 18:50
Hot topic Hardware requirements for Xeon Phi Coprocessor hosting system
by Jakob L.
Wed, 12/12/2012 - 09:05 15
by jimdempseyatthecove
Thu, 10/24/2013 - 08:36
Normal topic AES performance on MIC
by Yordan Lazarov
Thu, 12/13/2012 - 03:59 4
by Taylor K. (Intel)
Tue, 01/15/2013 - 16:21
Normal topic Any details about the physical address and cache line mappings?
by Mikael P.
Wed, 12/19/2012 - 06:23 2
by Taylor K. (Intel)
Thu, 01/17/2013 - 09:03
Normal topic OpenMP Tasks + Offload possible?
by ds534486
Wed, 12/19/2012 - 08:08 5
by Kevin Davis (Intel)
Fri, 02/08/2013 - 05:07
Normal topic FAQs: Compiler
by Sumedh Naik (Intel)
Mon, 12/31/2012 - 13:30 0
by Sumedh Naik (Intel)
Mon, 12/31/2012 - 13:30
Normal topic VTune Amplifier for MPSS 4982
by Tim Prince
Wed, 01/02/2013 - 09:31 5
by Tim Prince
Wed, 01/16/2013 - 04:44
Normal topic Building the packaged binutils/gcc/glibc
by David F.
Wed, 01/02/2013 - 11:51 1
by Frances Roth (Intel)
Wed, 01/02/2013 - 12:33
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For more complete information about compiler optimizations, see our Optimization Notice.