Intel® Developer Zone:
Intel® Many Integrated Core Architecture (Intel MIC Architecture)

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Intel® Xeon Phi™

Intel® Xeon Phi™ Coprocessor is the brand name for all Intel® Many Integrated Core Architecture (Intel MIC Architecture) based products. At the end of 2012, Intel launched the first generation of the Intel Xeon Phi product family (coprocessors codenamed "Knights Corner") complementing the existing Intel® Xeon® processor product families to deliver new levels of performance for highly parallel workloads.

This forum is for discussion of public information about Intel MIC Architecture, Intel Xeon Phi Coprocessors, and preparing code to fully utilize this class of machines whether on a single chip or not (this is the key to programming the coprocessor).

Please visit the Developer zone at http://software.intel.com/mic-developer to see all documentation resources available for assessing, configuring, programming, and optimizing for Intel Xeon Phi Coprocessors.

Questions will be answered by both peers and Intel representatives that monitor this forum.

We invite you to subscribe to this forum to see new threads and updates (see button below, on the right). Please also note the ability to search for specific information within this forum, by clicking the button below, on the left.

Topic / Topic starter Post date Replies Last Post
Normal topic How to disassemble with objdump for programs running on mic
by yuyinyang
Sat, 11/22/2014 - 04:58 2
by Kevin Davis (Intel)
Tue, 12/02/2014 - 08:46
Normal topic Expected MIC core utilization
by Vladimir S.
Tue, 01/07/2014 - 16:14 6
by jimdempseyatthecove
Wed, 01/08/2014 - 14:21
Normal topic A weird linker error with _mm512_storenr_ps intrinsic in offload mode
by Hien P.
Wed, 03/18/2015 - 22:27 5
by Hien P.
Sun, 04/12/2015 - 22:36
Normal topic Offload error
by Cheng C.
Wed, 02/19/2014 - 13:24 2
by Charles Congdon...
Tue, 02/25/2014 - 13:22
Normal topic icpc generates vector instructions for normal C++ and causes crashes
by Teodor P.
Wed, 05/15/2013 - 11:12 4
by James Cownie (Intel)
Mon, 05/20/2013 - 09:30
Normal topic Intel Phi Stress Utility
by Joey d.
Tue, 08/19/2014 - 10:23 1
by loc-nguyen (Intel)
Mon, 08/25/2014 - 10:54
Normal topic packed store operation for vectorization on MIC
by conor p.
Wed, 09/10/2014 - 20:56 7
by jimdempseyatthecove
Fri, 11/14/2014 - 20:17
Normal topic MKL function load error: cpu specific dynamic library is not loaded.
by Peter B.
Wed, 08/07/2013 - 15:32 13
by loc-nguyen (Intel)
Wed, 08/28/2013 - 15:35
Normal topic Accessing files through micnativeloadex
by genis.aguilar
Thu, 02/07/2013 - 08:09 6
by Frances Roth (Intel)
Tue, 02/12/2013 - 16:46
Normal topic Rebuilding MPSS-3.2 (Yocto) release from source
by René O.
Tue, 04/08/2014 - 02:21 7
by Evan Powers (Intel)
Mon, 04/28/2014 - 17:37
Normal topic New user in MIC cluster
by Bsc Cns
Wed, 07/03/2013 - 01:08 5
by Bsc Cns
Tue, 07/09/2013 - 02:09
Normal topic aligning arrays on 64 byte boundaries for use on MIC
by conor p.
Mon, 06/09/2014 - 19:44 1
by Kevin Davis (Intel)
Wed, 12/03/2014 - 00:44
Hot topic vectorization intensity 0.0 in SIMD vectorized loop for MIC application
by conor p.
Mon, 11/03/2014 - 14:12 21
by jimdempseyatthecove
Fri, 11/07/2014 - 04:01
Normal topic SSE/SSE2 Instructions and the easiest way to port.
by Ozan S.
Sun, 10/13/2013 - 18:11 6
by george@fovia.com
Sun, 10/27/2013 - 11:23
Normal topic type OS windows question
by remy b.
Thu, 12/19/2013 - 00:00 2
by jimdempseyatthecove
Thu, 12/19/2013 - 09:30
Normal topic Problem with _Cilk_shared and big sized data
by Jesmin Jahan T.
Sun, 04/07/2013 - 13:36 1
by Sumedh Naik (Intel)
Mon, 04/08/2013 - 08:35
Normal topic Compiling mpss-3.4.3 from source code on Linux kernel 3.14 and above
by Xuhao C.
Thu, 02/26/2015 - 23:48 5
by Anselm B.
Mon, 03/09/2015 - 03:12
Normal topic Problem building for MIC as build process needs to execute binaries
by Fiona R.
Thu, 05/02/2013 - 08:05 7
by Olli-Pekka L.
Wed, 05/22/2013 - 00:47
Normal topic Symmetric MPI run
by George H.
Thu, 07/24/2014 - 15:15 5
by loc-nguyen (Intel)
Fri, 08/01/2014 - 16:28
Normal topic Offload mode and configure script.
by Mateusz M.
Thu, 07/18/2013 - 15:53 4
by Kevin Davis (Intel)
Tue, 11/19/2013 - 05:01
Normal topic Any details about the physical address and cache line mappings?
by Mikael P.
Wed, 12/19/2012 - 06:23 2
by Taylor Kidd (Intel)
Thu, 01/17/2013 - 09:03
Normal topic LINPACK results
by Fuad O.
Tue, 03/25/2014 - 02:08 5
by JJK
Thu, 04/16/2015 - 22:50
Normal topic STREAM in malloc-ed arrays
by Andrey Vladimirov
Sun, 06/23/2013 - 12:30 8
by Andrey Vladimirov
Tue, 06/25/2013 - 12:11
Normal topic simple questions
by Jen B.
Tue, 10/21/2014 - 07:46 3
by Jen B.
Tue, 10/21/2014 - 12:33
Normal topic Intel® Xeon® Processors & Xeon® Phi™ Coprocessors Webinars Sept 24,25 and October 8, 9
by kathy-farrel (Intel)
Mon, 09/23/2013 - 16:07 0
by kathy-farrel (Intel)
Mon, 09/23/2013 - 16:07
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For more complete information about compiler optimizations, see our Optimization Notice.