Store Buffer Forwarding Restriction on Size

Store Buffer Forwarding Restriction on Size


In reading section3.6.5.1 of the most recentIntel 64 and IA-32ArchitecturesOptimization Reference Manual, it seems that for theIntel Core microarchitecture a large load after a small store never stalls (for example, a word aligned 32 bit load after an 8 bit store). Am I interpreting it correctly?

Thank you,
Duarte Nunes

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For more complete information about compiler optimizations, see our Optimization Notice.

But that pertains to theIntel NetBurst microarchitecture. I know the document says "Fixing store-forwarding problems for Intel NetBurst microarchitecture generally also avoids problems on Pentium M, Intel Core Duo and Intel Core 2 Duo processors", but I want to induce the "problem" (to avoid using a memory barrier), so I'm asking about the Intel Core microarchitecture (specifically, about the contents ofTable 3-2).

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