Per Intel 64 and IA-32 Architectures Software Developers Manual Volume 3 (System Programming Guide)
8.2.2 Memory Ordering in P6 and More Recent Processor Families:
A) Reads are not reordered with other reads.
B) Writes are not reordered with older reads.
C) Writes to memory are not reordered with other writes
D) Reads may be reordered with older writes to different locations but not with older writes to the same location.
Based on the above, will the following act as full memory barrier
push eax #1 store
pop eax #2 load
Seems like based on the above rules:
1) #1 and #2 - no reorder per (D)
2) old/new reads - no reorder with #2 per (A)
3) old writes - no reorder with #1 per (C)
4) new writes - no reorder with #1 and #2 per (C) and (B)
Can the above act like the 'mfence' instruction? Is it as expensive?