Cache coherency protocol

Cache coherency protocol

I am interested to know some information regarding the cache cohency protocol used in Intel q9550(Yorkfield) and Harpertown machines, for example, which protocol is used, overhead of the cache coherency (snooping, invalidation) operations. I have looked up in the Internet, but did not get these specific details. I will be thankful if anyone can give any insight.

Thanks,
Tanima.

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For more complete information about compiler optimizations, see our Optimization Notice.

Tanima,

Often the documentation you need is hard to find. Intel needs to extend some effort in cataloging their documentation (and making the catalog easy to find).

Lacking that, use Google, enter in the search phrase

Architectures Optimization site:intel.com

The top item in my search is a .PDF document titled:

Intel 64 and IA-32 Architectures Optimization Reference Manual

Order Number: 248966-023

January 2011

Chapter 2.2.4 should get you started.

Once you get familiar with how to locate the correct document (where to find, how to search), then you will be able to find the answers to your questions.

Jim Dempsey

www.quickthreadprogramming.com

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