RCU+SMR, hazard pointers without memory barriers

RCU+SMR, hazard pointers without memory barriers

quick test before I spend another half hour typing in something that will disappear.

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There was some discussion here

I won't retype in my original post so as to not tempt the
activex daemons that lurk in Intel's html. :)

You can find a working prototype at
in the fastsmr package. It works on Linux for ia32 and for OS X for 32 bit powerpc. On a 866 mhz P3 a hazard pointer load with memory barriers is about 78 nsec and without memory barriers is about 11 nsec. On a 1.2 ghz ppc it's 115 and 10 nsec respectively. Not too bad when you let the pipelining do its stuff. This is probably the fastest lock-free read access method around that will scale well in a multiprocessor environment.

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