A couple of memory model questions

A couple of memory model questions

Can loads pass subsequent stores? Can a load from a storage location different than that of a subsequent load occur after the store? For example if the load location isn't in cache and the store location is in cache.

If yes, then I guess you need an MFENCE as a memory barrier to a store.release operation unless your prior accesses were just stores.

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Joe -

I'm no expert at this kind of thing, so I went to someone that knows more than I. Here is his answer to your questions:

Id recommend that they read http://www.intel.com/design/itanium/downloads/25142901.pdf if they have not already. (Though by the terminology they are using, they may have already read it.)

I believe that the answer to the question is that loads can pass subsequent plain stores to a different location. But a load may not pass a subsequent store.release. So just a store.release should be necessary, not a full MFENCE, though from the question it is not clear what the questioner is trying to do exactly.

--clay


though from the question it is not clear what the questioner is trying to do exactly.

I believe he is trying to figure how many MFENCE instructions are needed for an IA-32/64 implementation of SMR.

My implementation uses an MFENCE to prevent IA-32 from reordering the load, after store to another location case. I think we may need an extra MFENCE when you store into a hazard pointer that was null. Joe pointed this out on comp.programming.threads.

You should not need MFENCE instructions with your lock free code. On x86 architecture LFENCE/SFENCE/MFENCE instructions are only used in combination with MOVNTDQ/MOVNTPD/MOVNTI/MASKMOVDQU.Since your code dos not use SSE instructions memory fences are not necessary. See IA-32 Intel Architecture Software Developer's Manual, Volume 1, Chapter 11.4.4 for more details.

Quoting - rshpount You should not need MFENCE instructions with your lock free code. On x86 architecture LFENCE/SFENCE/MFENCE instructions are only used in combination with MOVNTDQ/MOVNTPD/MOVNTI/MASKMOVDQU. Since your code dos not use SSE instructions memory fences are not necessary. See IA-32 Intel Architecture Software Developer's Manual, Volume 1, Chapter 11.4.4 for more details.

This is just not correct. LFENCE and SFENCE are really not necessary. But MFENCE is necessary in some situations, even if SSE is not used.

The main (the only?) source of reorderings in x86 is store buffer. In order to "neutralize" store buffer one have to use MFENCE.

One of the most famous examples where MFENCE is needed on x86 is Peterson's mutual exclusion algorithm:

http://en.wikipedia.org/wiki/Peterson%27s_algorithm

One can see details of x86 ordering rules in "Intel 64 Architecture Memory Ordering White Paper":

http://developer.intel.com/products/processor/manuals/318147.pdf

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