I've found a strange phenomenon with Sandy-Bridge processors and am curious if anyone can answer why this occurs.
If you enable SMT in the bios, power consumption when idle (running sleep) on the system increases by .3%-1% (depending on system). These measurements come from running on dual-socketed Sandy-Bridge stand-alone servers and rack-based servers using a Watts-Up Pro device. (Turbo is disabled in both cases.) Are additional resources being powered when SMT is enabled in the bios?
When running parallel benchmarks (NAS Parallel OpenMP), but only using as many threads as physical cores (16 in this case, 2 sockets, each 8-core Sandy-Bridge), I see a power increase of 2-3% with SMT enabled (in bios) over SMT disabled (in bios). Using Intel's performance monitoring tools (pcm.x), I see L2 and L3 misses increase with SMT enabled over SMT disabled for some benchmakrs. Using a custom tool for reading performance counters using PAPI, I find icache misses also increase sizably for a number of the parallel benchmarks. Although these additional misses impact power, they rarely impact performance (max negative impact is ~.5% for the NPBs). The increase in icache misses (and subsequently L2/L3 misses) leads me to suspect that enabling SMT in the bios causes some form of icache resource partitionining between threads. (This seems reasonable given the literature on resource partitioning to improve SMT performance.)
My questions are: 1) Is resource partitiioning occurring (am I on the right track)? 2) Why would resource partitioning occur even if there is not active second thread? and 3) What is being enabled/disabled to cause idle power consumption to increase when SMT is enabled in the bios?
Thank you in advance,