I'm trying to build a "topology graph" for an Intel CPU (in this case an i7-3770, but I may need to do the same for other CPUs), where each logical core is represented by a vertex, and edges indicate communication channels between cores. These edges should be labeled with bandwidth and latency values.
I can see two ways of generating such a graph. The first would be to assume that the graph is fully connected, and then obtain edge labels by using cache access latency and bandwidth values (e.g. logical cores sharing the same physical core would be connected via the L1 cache, and logical cores on different physical cores would have edge labels based on L3 access times).
The second method, which seems like it would be more representative of the reality of the hardware, would be to use information concerning the cache coherence network when building the graph. From my understanding, Intel chips use a ring topology for this network, which is quite different than the fully-connected network I would have to use if I followed the first method. However, I have been unable to find latency and bandwidth values for the data lines (as opposed to channels reserved for management messages) of the cache coherence network. Is this data publicly available and, if so, where might I find it?
This second approach raises the question of what values to use when labeling edges between logical cores that share the same physical core. My first guess would be to use the L1 cache latency and bandwidth, but I'm not sure if that would be the best solution. Does anyone have any suggestions on what might be a better source of values for these edges?