Hello. I'm still new to intel architecture and the question might be kind of silly. But anyway, I'm looking for some specification of cache coherence protocol for Haswell. AFAIK it uses MESIF, but I'm concerned about corner cases like:
1. Two cores try to modify the same cache line "simultaneously". Who will win? Can both lose? How does intel implementatio handle this case?
2. One core try to read from a memory location which is not in cache while another one has exclusive ownership of a cache line with this memory location and try to write some value into it (simultaneously). Who will win? The cache line state will first transfered to a Shared state and then invalidated or Modified and then Shared?
How does intel cache coherence inplementation handle such cases?