Intel® Developer Zone:
Intel® Moderncode for Parallel Architectures

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Tap our experts and your peers to help meet the challenge of developing applications on modern hardware. This is the place to ask questions (and get answers) related to all aspects of parallel programming on Intel® Architecture.

This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Hot topic parallel parallel for overhead in OpenMP
by mjc
Fri, 05/24/2013 - 11:42 22
by lara h.
Wed, 10/02/2013 - 03:56
Normal topic algorithms
by lara h.
Wed, 10/02/2013 - 03:50 0
by lara h.
Wed, 10/02/2013 - 03:50
Normal topic Intel TSX implementation properties
by krahnack
Tue, 07/23/2013 - 19:38 7
by Rolf Andersson
Sun, 09/29/2013 - 01:58
Normal topic Parallelizing my existing code in TBB please help me with this errors
This topic has been moved to "Intel® Threading Building Blocks" (View topic)
Normal topic Why Sequential Semantic on x86/x86_64 is using through MOV [addr], reg + MFENCE instead of +SFENCE?
by AlexeyAB
Thu, 09/26/2013 - 04:06 0
by AlexeyAB
Thu, 09/26/2013 - 04:06
Normal topic cache topology
by Ilya Z.
Tue, 08/20/2013 - 12:23 13
by iliyapolak
Thu, 09/26/2013 - 01:23
Normal topic Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
by Kathy F. (Intel)
Fri, 09/13/2013 - 16:34 0
by Kathy F. (Intel)
Fri, 09/13/2013 - 16:34
Hot topic Overhead of HLE acquire and release
by Rolf Andersson
Sat, 07/27/2013 - 08:58 24
by jimdempseyatthecove
Wed, 09/04/2013 - 06:02
Normal topic Selecting custom victim in job scheduling on NUMA systems
by kadir
Thu, 08/29/2013 - 00:32 1
by jimdempseyatthecove
Thu, 08/29/2013 - 12:29
Normal topic MPI+OPENMP does not speed up
by Siwei D.
Mon, 02/04/2013 - 06:55 10
by Siwei D.
Thu, 08/22/2013 - 03:52
Normal topic Poor openmp performance
by Ronglin J.
Thu, 08/15/2013 - 20:53 5
by Ronglin J.
Sun, 08/18/2013 - 20:17
Normal topic how to measure false sharing on intel xeon e7520 cpu
by Xingjing Lu
Wed, 08/14/2013 - 02:14 0
by Xingjing Lu
Wed, 08/14/2013 - 02:14
Normal topic Help with web Socket jsp.
by JudLup Luna
Wed, 07/31/2013 - 10:34 1
by JudLup Luna
Wed, 07/31/2013 - 10:35
Normal topic runtime of functions
by Bernhard
Wed, 07/17/2013 - 08:58 3
by Dmitry Kuzmin (...
Mon, 07/22/2013 - 00:30
Normal topic NUMA and Linux Page Cache
by Black.S
Thu, 06/27/2013 - 06:55 5
by Black.S
Sun, 07/07/2013 - 09:51
Normal topic cmpxchg16b
by jseigh
Tue, 09/28/2004 - 13:23 5
by jimdempseyatthecove
Fri, 06/28/2013 - 20:11
Normal topic Detecting CPU topology
by Ilya Z.
Sun, 05/12/2013 - 11:00 6
by Black.S
Thu, 06/27/2013 - 06:34
Normal topic Recommendations for Intel(r) Transactional Synchronization Extensions have been published
by Roman Dementiev...
Wed, 06/05/2013 - 02:29 11
by Sergey Kostrov
Tue, 06/25/2013 - 06:06
Normal topic Forcing termination of Win32 thread before its uantum expiration
by iliyapolak
Wed, 06/12/2013 - 07:21 11
by iliyapolak
Mon, 06/24/2013 - 01:01
Hot topic HYDT_bscu_wait_for_completion
This topic has been moved to "Intel® Clusters and HPC Technology" (View topic)
Normal topic lock xchg performance
by Brendon C.
Fri, 06/07/2013 - 22:06 13
by jimdempseyatthecove
Sat, 06/15/2013 - 05:42
Normal topic initialize common block defined in a module in OMP
by stydofe1
Wed, 06/12/2013 - 07:53 5
by Andrey Churbano...
Fri, 06/14/2013 - 02:13
Normal topic Threads Under Performing (OMP/PTheads)
by Darren S.
Tue, 06/11/2013 - 17:17 2
by jimdempseyatthecove
Wed, 06/12/2013 - 05:41
Normal topic Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
by Roman Dementiev...
Fri, 06/07/2013 - 06:56 4
by jimdempseyatthecove
Mon, 06/10/2013 - 05:03
Normal topic L3 Cache Mapping on Nehalem (Xeon X3430)
by Michael G.
Thu, 05/23/2013 - 12:24 2
by Sergey Kostrov
Sun, 05/26/2013 - 22:05
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Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.