TITLE: Bus Lock
Cycles that a BUS LOCK is asserted on the bus. A common atomic lock will not be transferred to a bus lock except in exceptional circumstances of either the memory of the lock residing in uncacheable memory or if the lock extends beyond a cache line boundary splitting cache lines. Atomic lock instructions involve utilizing a lock prefix on the instruction and having the destination operand assigned to a memory address. The following instructions can run atomically with a lock prefix on current Intel processors: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG (does not require lock prefix.) A BUS lock would involve one of these instructions on an uncacheable area of memory or across to a cache line boundary.
Bus locks impact all architectures on all OS’s. Bus locks have a very high performance penalty of ~1000 cycles. It is highly recommended to avoid locks in uncacheable memory and to make sure the memory addresses of the locked are aligned.
Look at the atomic instruction causing the BUS LOCK and determine if it is an alignment or a uncacheable/USWC (uncacheable speculative write combining) issue.