TITLE: Back End Bound Due To Latency Caused In The Uncore
Cycles the Memory is bound on Uncore (i.e. anything outside the processor core: LLC, Memory, Ring, etc.)
This metric represents how often the pipeline was back end bound on the Uncore (i.e. anything outside the processor core: LLC, Memory, Ring, etc.). Avoiding cache misses (i.e. L2 misses) will improve the latency and increase performance.
For instance, if you have many L2 misses and hit in the LLC cache or need to go to main memory to fetch the data, you would see a high percentage of back end memory bound percentage in the Uncore.
EQUATION: CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD