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Intel® Performance Bottleneck Analyzer (Archived)

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The Intel® Performance Bottleneck Analyzer (Intel® PBA) framework can be used to identify and prioritize issues specific to current and future Intel® architectures. This forum should be used to discuss questions, issues, or usages for the framework.

For more information, please see:  http://software.intel.com/en-us/articles/intel-performance-bottleneck-analyzer/
This forum is archived and no longer monitored. You can search and read the content but cannot create new threads or post replies to existing threads.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Zero Length Calls
by Michael Chynowe...
Thu, 08/23/2012 - 10:03 0
by Michael Chynowe...
Thu, 08/23/2012 - 10:03
Normal topic Store Forward Block
by Michael Chynowe...
Thu, 11/01/2012 - 13:46 0
by Michael Chynowe...
Thu, 11/01/2012 - 13:46
Normal topic Uops from the Decoded ICache
by Charlie Hewett ...
Tue, 09/18/2012 - 16:32 0
by Charlie Hewett ...
Tue, 09/18/2012 - 16:32
Normal topic Port 4 Utilization
by Charlie Hewett ...
Thu, 09/20/2012 - 13:40 0
by Charlie Hewett ...
Thu, 09/20/2012 - 13:40
Normal topic MITE Micro-ops to IDQ
by Patrick Konsor ...
Fri, 08/24/2012 - 14:28 0
by Patrick Konsor ...
Fri, 08/24/2012 - 14:28
Normal topic Non flat segment load
by Rajshree Chabuk...
Fri, 12/07/2012 - 16:49 0
by Rajshree Chabuk...
Fri, 12/07/2012 - 16:49
Normal topic Front End Latency
by Charlie Hewett ...
Tue, 09/18/2012 - 16:38 0
by Charlie Hewett ...
Tue, 09/18/2012 - 16:38
Normal topic Bad Speculation Speculative Uops
by Charlie Hewett ...
Thu, 09/20/2012 - 13:51 0
by Charlie Hewett ...
Thu, 09/20/2012 - 13:51
Normal topic Cache line replacement study
by Michael Chynowe...
Mon, 09/03/2012 - 09:14 0
by Michael Chynowe...
Mon, 09/03/2012 - 09:14
Normal topic Front End Bandwidth
by Charlie Hewett ...
Tue, 09/18/2012 - 16:52 0
by Charlie Hewett ...
Tue, 09/18/2012 - 16:52
Normal topic Back End Bound Due To Latency Caused By L2 Cache
by Charlie Hewett ...
Thu, 09/20/2012 - 15:13 0
by Charlie Hewett ...
Thu, 09/20/2012 - 15:13
Normal topic Back End 0 Uops Executed
by Charlie Hewett ...
Thu, 09/20/2012 - 15:21 0
by Charlie Hewett ...
Thu, 09/20/2012 - 15:21
Normal topic BT CLEAR
by christine-lin (...
Fri, 09/07/2012 - 11:41 0
by christine-lin (...
Fri, 09/07/2012 - 11:41
Normal topic Back End Bound
by Charlie Hewett ...
Tue, 09/18/2012 - 17:06 0
by Charlie Hewett ...
Tue, 09/18/2012 - 17:06
Normal topic x87 Floating Point Store/Restore for Rounding
by Michael Chynowe...
Thu, 07/26/2012 - 13:03 0
by Michael Chynowe...
Thu, 07/26/2012 - 13:03
Normal topic Back End 3 Or More Uops Executed
by Charlie Hewett ...
Thu, 09/20/2012 - 15:26 0
by Charlie Hewett ...
Thu, 09/20/2012 - 15:26
Normal topic System Call Finder
by christine-lin (...
Mon, 09/10/2012 - 17:12 0
by christine-lin (...
Mon, 09/10/2012 - 17:12
Normal topic Port 0 Utilization
by Charlie Hewett ...
Thu, 09/20/2012 - 13:37 0
by Charlie Hewett ...
Thu, 09/20/2012 - 13:37
Normal topic Instruction Starvation
by Patrick Konsor ...
Fri, 08/17/2012 - 16:08 0
by Patrick Konsor ...
Fri, 08/17/2012 - 16:08
Normal topic AVX_TRANSITION
by Erik Niemeyer (...
Tue, 09/25/2012 - 09:36 0
by Erik Niemeyer (...
Tue, 09/25/2012 - 09:36
Normal topic SPIN_WAIT_NO_PAUSE - finder
by PRIYA V. (Intel)
Fri, 09/14/2012 - 12:41 0
by PRIYA V. (Intel)
Fri, 09/14/2012 - 12:41
Normal topic Port 3 Utilization
by Charlie Hewett ...
Thu, 09/20/2012 - 13:39 0
by Charlie Hewett ...
Thu, 09/20/2012 - 13:39
Normal topic Bus Lock
by Patrick Konsor ...
Fri, 08/24/2012 - 14:27 0
by Patrick Konsor ...
Fri, 08/24/2012 - 14:27
Normal topic 256 bit split load/store issues
by Rajshree Chabuk...
Fri, 12/07/2012 - 16:48 0
by Rajshree Chabuk...
Fri, 12/07/2012 - 16:48
Normal topic Uops from the Microcode Sequencer
by Charlie Hewett ...
Tue, 09/18/2012 - 16:36 0
by Charlie Hewett ...
Tue, 09/18/2012 - 16:36
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.