I am trying to profile L3 cache behaviour for two different architectures, and I encounter a lot of difficulties.
These two architectures are based on X7460 and X7560 Intel Xeon processors.
I am using VTune 9.1 and PTU 4.0 Update 3 to sample the events.
PTU gives me a list of available events for each architecture.
the X7400 series, I have many many events about L1 and L2 caches access
(load, store, self, both_cores, demand, prefetch). Actually, 30% of the
available events are about cache. But NOTHING about L3 cache.
For the X7500 series, I have some LLC (last level cache) events:
and a lot about LLC in OFFCORE_RESPONSE_0 events. But nothing clearly mentionning store or load...
My questions are:
the L3 cache events exist? Is it just PTU and VTune which do not know
where to search, and it is possible to physically interrogate some
registers? Or L3 caches are too complicated now, and Intel just dropped
the L3 cache evaluation?
- what do you use to profile L3 cache events?
- Since which architecture the L3 are sorely accessible?