to avoid false-sharing,need to add some 'pad' data between / before / after theshare variable,
I have checked the TBB code, it define ALIGNED_SIZE 64 (64 is common size of cache line),
will the cache linesize vary with different CPU platform? i.e. Core2 ,XEON,and XEON 5500?
ps:Core2 has 64Kcache while XEON has 2M,right?