I've been reading my cache and processor material. My understanding is that there are multiple cache lines, each wired for specific memory regions. Is that accurate?
Would I be correct in saying that, if I were to distribute my data structure in memory properly I could use multiple cache lines at the same time? Would it happen that each of these cache lines pre-fetches memory as well? I might have misunderstood something, but it seems to me that if I were to use memory regions properly I could effectively have multiple cache lines in the processor at the same time, suggesting that I could use multiple cache lines in my algorithm to increase performance.
Is my understanding accurate?