Can somebody explain to me in plain english the problem with DTLB Page Walks.
I seem to have a confusion with it.
Basically I have a slide that states to "Check Paging Issues"
- Measure density of data access pattern with respect to 4K page
- Reads From the processor / DTLB Page Walks
- A good number is 64
o 4K/cache line size = 4K/64 bytes = 64
- Low value indicates data access pattern is inefficient
oIncur frequent DTLB miss penalty
oCan cause excess memory traffic
I have some problems swallowing this one...
Thanks in advance