Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
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Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Why behavior of L2 adjacent line prefetcher are different in Core2Duo and Core-i7 ?
by Roy, Bholanath
Thu, 12/13/2018 - 07:33 11
by Roy, Bholanath
Wed, 03/13/2019 - 08:49
Normal topic Platforms with an exposed debug interface for sampling registers.
by Gottschall, Bjoern
Wed, 03/13/2019 - 07:50 0
by Gottschall, Bjoern
Wed, 03/13/2019 - 07:50
Normal topic How to obtain PEBS data linear address and latency value from the perf report?
by kundnani, harsh
Mon, 03/11/2019 - 13:15 4
by Hadi Brais
Tue, 03/12/2019 - 11:16
Normal topic Calculating L2 <-> L3/MEM bandwidth on Intel Skylake SP
by Thomas R.
Wed, 03/28/2018 - 07:24 8
by Hadi Brais
Mon, 03/11/2019 - 12:31
Normal topic How to narrow down intel PCM data to a single process?
by Gholamipour, Amir
Mon, 03/04/2019 - 16:17 1
by Hadi Brais
Tue, 03/05/2019 - 14:00
Normal topic Difference between cache banks and cache slices
by anthony b.
Fri, 08/05/2016 - 23:50 9
by McCalpin, John
Mon, 03/04/2019 - 17:13
Normal topic Why are the results of rdmsr not consistency
by Zhou, Fang
Thu, 02/28/2019 - 23:00 11
by Travis D.
Mon, 03/04/2019 - 14:21
Normal topic How many MSRs can I use
by Zhou, Fang
Thu, 02/28/2019 - 11:59 2
by Zhou, Fang
Fri, 03/01/2019 - 14:58
Hot topic Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?
by Stephen
Fri, 10/03/2014 - 11:29 36
by Travis D.
Fri, 03/01/2019 - 09:40
Normal topic Intel MBM per NUMA node bandwidth usage info
by Reza
Sat, 02/23/2019 - 21:30 1
by Hadi Brais
Thu, 02/28/2019 - 12:03
Normal topic Instruction prefetcher - missing from Optimization Manual
by Russell Van Zandt
Wed, 02/27/2019 - 12:18 2
by Travis D.
Thu, 02/28/2019 - 10:01
Normal topic 4th gen (Haswell) undocumented events?
by nsmeds
Thu, 06/27/2013 - 03:37 13
by Travis D.
Thu, 02/28/2019 - 00:59
Normal topic Mcelog in linux doesnt show the exact DIMM location for ECC/UECC error
by Kishore, Nanda
Tue, 02/26/2019 - 22:10 0
by Kishore, Nanda
Tue, 02/26/2019 - 22:10
Normal topic How can a fence in progress inhibit triggering L1 hardware prefetching?
by Hadi Brais
Sat, 02/23/2019 - 09:56 0
by Hadi Brais
Sat, 02/23/2019 - 09:56
Normal topic OpenGL 3.3
by kova, tina
Fri, 02/22/2019 - 11:21 0
by kova, tina
Fri, 02/22/2019 - 11:21
Normal topic How is the collection of MSR registers
by Black.S
Tue, 12/10/2013 - 09:30 14
by McCalpin, John
Wed, 02/20/2019 - 15:00
Normal topic MSRs to query processor settings
by Johannes Hofmann
Tue, 02/19/2019 - 04:40 1
by McCalpin, John
Tue, 02/19/2019 - 09:02
Hot topic How to read performance counters by rdpmc instruction?
by Sergey Shalnov ...
Wed, 10/07/2015 - 22:01 29
by McCalpin, John
Tue, 02/12/2019 - 07:41
Normal topic Skylake (i7-7980XE) IOMMU and uncore_iio_x
by mei, guodong
Mon, 02/11/2019 - 05:19 0
by mei, guodong
Mon, 02/11/2019 - 05:19
Normal topic PMU events for Cannonlake
by Travis D.
Thu, 01/31/2019 - 19:24 3
by McCalpin, John
Mon, 02/04/2019 - 11:43
Normal topic Utilization vs. C0 Residency
by Omer B. (Intel)
Thu, 01/31/2019 - 07:17 1
by McCalpin, John
Thu, 01/31/2019 - 09:15
Normal topic Confusion about RDPMC, RDMSR and addresses
by Silvia
Mon, 01/28/2019 - 08:13 6
by Silvia
Wed, 01/30/2019 - 04:50
Normal topic SKL - strange memory behavior
by Aric H.
Mon, 01/28/2019 - 08:48 1
by McCalpin, John
Mon, 01/28/2019 - 10:53
Normal topic How to program IIO_LLC_WAYS in Skeylate CPU?
by mei, guodong
Mon, 01/28/2019 - 06:11 0
by mei, guodong
Mon, 01/28/2019 - 06:11
Normal topic pcie bandwidth drops on Skylake-SP
by Friedhelm S.
Tue, 08/15/2017 - 08:25 2
by mei, guodong
Sun, 01/27/2019 - 06:33
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For more complete information about compiler optimizations, see our Optimization Notice.