Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

Announcements
 
Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Xeon D1541 is losing PCIe packets
by mei, guodong
Tue, 01/09/2018 - 17:25 1
by mei, guodong
Sun, 01/21/2018 - 15:53
Hot topic Is there an energy profiling tool to monitor CPU power consumption on Linux?
by Iulia S.
Sat, 12/02/2017 - 13:46 15
by Travis D.
Sun, 01/21/2018 - 13:00
Normal topic MCDRAM and DDR4 Performance Counter Xeon Phi
by Chetan Arvind Patil
Thu, 01/18/2018 - 10:45 6
by Chetan Arvind Patil
Sat, 01/20/2018 - 16:44
Normal topic FPGA sending Interrupts to CPU
by Stojkov, Nikola
Fri, 01/19/2018 - 05:56 0
by Stojkov, Nikola
Fri, 01/19/2018 - 05:56
Normal topic How does the performance counter of a logical cpu collect the prefetcher-related event with hyperthreading enabled?
by hiratz s.
Sat, 01/13/2018 - 18:00 6
by hiratz s.
Thu, 01/18/2018 - 16:52
Normal topic memory bandwidth measurements for Quad-Core Intel® Atom™ E3845
by vu, yogesh
Thu, 01/18/2018 - 08:25 0
by vu, yogesh
Thu, 01/18/2018 - 08:25
Normal topic Accessing uncore_qpi in Intel E5-4610 V2
by dhumal, akshay
Thu, 01/04/2018 - 19:59 9
by McCalpin, John
Wed, 01/17/2018 - 10:30
Normal topic Calculating Memory Bandwidth using perfmon2
by Shuja-ur-Rehman B.
Thu, 04/14/2016 - 03:44 1
by dhumal, akshay
Mon, 01/15/2018 - 03:15
Normal topic Accessing Uncore performance counters
by Priyadarshi
Fri, 10/19/2012 - 14:44 8
by dhumal, akshay
Mon, 01/15/2018 - 03:06
Normal topic AES NI performance optimization
by r, rani
Thu, 01/11/2018 - 02:38 0
by r, rani
Thu, 01/11/2018 - 02:38
Hot topic temporary pcie bandwidth drops on Haswell-v3
by Friedhelm S.
Tue, 11/24/2015 - 04:34 23
by mei, guodong
Tue, 01/09/2018 - 16:46
Normal topic What is IO directory cache(IODC) used for?
by AARONMJ L.
Tue, 01/02/2018 - 20:57 0
by AARONMJ L.
Tue, 01/02/2018 - 20:57
Normal topic Why these BIOS options will impact RDMA performance
by AARONMJ L.
Tue, 12/26/2017 - 18:51 0
by AARONMJ L.
Tue, 12/26/2017 - 18:51
Hot topic Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?
by Stephen
Fri, 10/03/2014 - 11:29 27
by McCalpin, John
Sun, 12/24/2017 - 12:53
Normal topic PrefetchT0
by Madhav A.
Wed, 01/29/2014 - 11:11 9
by Travis D.
Sun, 12/24/2017 - 11:11
Normal topic TLB Miss or Fill event
by Kelvin C.
Tue, 12/19/2017 - 00:21 0
by Kelvin C.
Tue, 12/19/2017 - 00:21
Normal topic What hardware is making my consecutive loop times slow?
by Franks, Brandon
Thu, 12/14/2017 - 06:50 1
by Travis D.
Mon, 12/18/2017 - 22:18
Normal topic What is the replacement policy of L2 and L3 on BroadWell CPU?
by Zeke W.
Thu, 12/14/2017 - 01:15 2
by Travis D.
Mon, 12/18/2017 - 22:11
Normal topic DMA scans with I/OAT have inconsistent results
by Timo D.
Tue, 12/05/2017 - 04:41 2
by Timo D.
Wed, 12/13/2017 - 01:01
Normal topic Broadwell dual-socket core labels?
by Clay B.
Tue, 12/05/2017 - 16:21 3
by McCalpin, John
Thu, 12/07/2017 - 08:28
Hot topic HowTo MSR for Turbo Ratios ?
by CyrIng
Thu, 01/09/2014 - 10:33 42
by CyrIng
Fri, 12/01/2017 - 16:00
Normal topic Hide DRAM latency with concurrent access
by Vaclav L.
Thu, 11/30/2017 - 15:41 1
by McCalpin, John
Fri, 12/01/2017 - 07:37
Normal topic PEBS sample context
by rp
Thu, 11/30/2017 - 12:48 0
by rp
Thu, 11/30/2017 - 12:48
Normal topic move_pages() flush TLB once or multiple times?
by kai w.
Thu, 11/30/2017 - 00:37 0
by kai w.
Thu, 11/30/2017 - 00:37
Normal topic Why should data be aligned to 16 bytes for SSE instructions?
by Member, Forum
Mon, 11/27/2017 - 17:36 4
by Tim P.
Tue, 11/28/2017 - 15:19
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.