Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic How to measure remote read or write request of a core using PMU?
by Duan Z.
Mon, 02/20/2017 - 17:54 2
by Duan Z.
Tue, 02/21/2017 - 17:06
Normal topic Package C-state Residency Counters
by CyrIng
Tue, 02/21/2017 - 09:51 0
by CyrIng
Tue, 02/21/2017 - 09:51
Normal topic Get Very Low Performance with MP Linpack benchmark in HPC cluster
by Minh C.
Mon, 02/20/2017 - 20:26 0
by Minh C.
Mon, 02/20/2017 - 20:26
Normal topic Does msync come with a cache flushing operation
by kai w.
Fri, 02/17/2017 - 15:52 0
by kai w.
Fri, 02/17/2017 - 15:52
Normal topic DDR2 & DDR3 timings similarities
by CyrIng
Wed, 02/15/2017 - 07:51 5
by CyrIng
Fri, 02/17/2017 - 10:43
Normal topic It is possible to monitor cross-processes using RDTSC or RDTSCP?
by Zirak
Thu, 02/16/2017 - 13:37 1
by McCalpin, John
Fri, 02/17/2017 - 08:47
Normal topic Capturing multiple events simultaneously using RDPMC instruction
by Zirak
Thu, 02/16/2017 - 08:47 3
by McCalpin, John
Fri, 02/17/2017 - 08:05
Hot topic How to read performance counters by rdpmc instruction?
by Sergey Shalnov ...
Wed, 10/07/2015 - 22:01 27
by Zirak
Thu, 02/16/2017 - 20:44
Normal topic event to count access memory and PAPI
by Abdo L.
Thu, 02/16/2017 - 13:39 0
by Abdo L.
Thu, 02/16/2017 - 13:39
Normal topic Using RAPL to read PP0 and DRAM energy on haswell
by Sameer A.
Tue, 04/05/2016 - 15:47 8
by McCalpin, John
Tue, 02/14/2017 - 09:36
Normal topic CPU supports clwb and clflushopt
by kai w.
Mon, 02/13/2017 - 00:45 1
by McCalpin, John
Mon, 02/13/2017 - 09:23
Normal topic Write Combining Buffer Out of Order Writes and PCIe
by bmeardon
Tue, 02/07/2017 - 11:52 9
by bmeardon
Mon, 02/13/2017 - 09:22
Normal topic My summary of clflush and clflushopt.
by Steven H.
Sun, 02/12/2017 - 13:28 1
by McCalpin, John
Mon, 02/13/2017 - 09:07
Normal topic Measure uncore frequency on my Skylake CPU
by Travis D.
Wed, 02/01/2017 - 14:10 2
by Thomas R.
Mon, 02/13/2017 - 05:23
Normal topic Configure and read iMC Performance Counters with Haswell E5 and missing /sys/devices/ export
by Stephan W.
Thu, 01/19/2017 - 11:00 5
by McCalpin, John
Thu, 02/09/2017 - 09:46
Normal topic Concurrency support of CLFLUSH
by Steven H.
Mon, 02/06/2017 - 15:30 1
by McCalpin, John
Tue, 02/07/2017 - 13:24
Normal topic Effect of DVFS on memory load latency information using PEBS on Haswell
by sridutt
Thu, 02/02/2017 - 20:14 3
by McCalpin, John
Mon, 02/06/2017 - 14:24
Normal topic Disabling turbo boost for only some cores on a socket
by Travis D.
Tue, 01/31/2017 - 14:00 4
by Travis D.
Fri, 02/03/2017 - 12:17
Normal topic The sample code for capping power consumption by RAPL interface/driver
by Kevin
Mon, 01/09/2017 - 18:19 1
by sridutt
Thu, 02/02/2017 - 22:11
Normal topic RAPL - Per Core Power Measurement / Capping
by Dave W.
Mon, 06/13/2016 - 08:43 6
by sridutt
Thu, 02/02/2017 - 21:45
Normal topic Intel Memory Latency Checker V3.0 released
by Thomas Willhalm...
Wed, 11/11/2015 - 11:50 5
by Travis D.
Thu, 02/02/2017 - 12:17
Normal topic Performance prediction for floating-point heavy kernel
by Porter, Andrew
Fri, 12/02/2016 - 08:37 7
by Travis D.
Tue, 01/31/2017 - 19:01
Normal topic Reading programmable and fixed-function performance counters
by Davidson F.
Mon, 01/02/2017 - 18:12 9
by Davidson F.
Tue, 01/31/2017 - 16:13
Normal topic Intel(r) Energy Checker SDK. (ESRV Service queencreek) - Huge problems!
by sean vreeland
Sat, 12/24/2016 - 07:22 3
by Andrew C.
Tue, 01/31/2017 - 01:27
Normal topic Page-Based Memory Types and L1 Cache
by Urs M.
Mon, 01/30/2017 - 07:11 1
by McCalpin, John
Mon, 01/30/2017 - 10:39
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Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.