referring to "xeons" (nehalem, Westmere, SB) operating in the Intel64
"IA-32e Protected" and "Paging" mode (full 64-bit support, see http://download.intel.com/products/processor/manual/325384.pdf Vol3A) data in the "Memory Management" data structures (p2-8 Vol 3A) used in the effective to physical address translation mechanisms (p4-28 Vol 3A) can be cached by actual H/W: Section 4.10 "CACHING TRANSLATION INFORMATION" : "A processor may cache information from the paging-structure entries in TLBs and paging-structure caches".
The concept of TLB h/w caching page table entries discussed in subsection 18.104.22.168 is well known and the documentation elsewhere clearly highlights the TLB structures for each different micro-architecture.
For "Paging Structure Caches" of Section 4.10.3, it is mentioned that "A processor may support any or all the following paging-structure caches: PML4, PDPTE and PDE.... " data structures.
Does any of Xeons (Nehalem, Westmere, Sandy-Bridge) support any "Page Structure Cache" H/W ? I have NOT been able to find any reference for such H/W existing on any of these processors.
Should I assume that this is feature that is permitted by the ISA spec but has NOT been implemented by any if these processors?
Otherwise, can I find any more specific information about this H/W per processor?
I would appreciate any information or pointer to it ....