Hello,I'm trying to measure TLB misses with the following counters:DTLB_LOAD_MISSES.ANYMEM_LOAD_RETIRED.DTLB_MISSThe second one gives more misses than the first one. And also the first one gives more misses (approximately 2 times) than the expected misses. What can be the possible reasons? Is the first one counting 2 times per miss for first level miss and second level miss? The machine I'm using is Xeon L5520. Any help is appreciated.Cheers,
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