These questions are about the 8 banks in the L1 data cache in Sandy Bridge.
Page 3-57 of Intel's Optimization Reference Manual says:
"A bank conflict happens when two simultaneous load operations have the same bit 2-5 of their linear address but they are not from the same set in the cache (bits 6-12)."
Page 2-22 of Intel's Optimization Reference Manual says:
"Since 16-byte loads can cover up to three banks, and two loads can happen every cycle, it is possible that six of the eight banks may be accessed per cycle, for loads. A bank conflict happens when two load accesses need the same bank (their address has the same 2-4 bit value) in different sets at the same time."
1. Which bits of the memory byte address select an L1 data cache bank?
Since 16-byte loads can cover up to three banks, I guess the data bus of each bank is 8 bytes wide. Bits 0-2 of a memory byte address would select a byte within the width of this data bus. It therefore seems to me that bits 3-5 of a memory byte address select the bank. I don't understand why the Optimization Reference Manual says the bank is selected by bits 2-5 on page 3-57 and bits 2-4 on page 2-22.
2. Do each of the 8 banks in the L1 data cache have a separate read port and write port or does each bank have a single combined read/write port? In other words, can a load and store access different addresses of the same bank in the same cycle?
3. Does an L1 cache bank need some number of idle cycles when switching between a load and a store? If yes, how many?