Sandybridge supports 1G byte page?

Sandybridge supports 1G byte page?

Hi,all.

Ifind sandy bridge's L1D DTLB support 1GB page in the table 2-9(64-ia-32-architectures-optimization-manual) .I tested my i7-2600 processor,and found it doesn't support 1GB page using CPUID instruction under ubuntu 11.04(64 bit version).
Also,I find the E3-12xx(sandy bridge based ) processors do not support this feature through google.
I want to know whethersandy bridge microarchitecturesupport 1G byte pageorjust an Intel's lie.

If anybody know,tell me.Thanks.

Ray Song

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For more complete information about compiler optimizations, see our Optimization Notice.
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The Optimization manual discusses a number of design feature in a given microarchitecture. It would be incorrect and unsafe for software to assume a particular feature designed in a microarchitecture will be present in all product skus or in all market segments.

To look up whether a specific processor feature is present for a given brand/sku, one can look up the corresponding data sheet for a particular processor brand/sku from www.intel.com by navigating to specific processor product page. Software can query the presence of specific hardware capability via various feature flag interfaces of the CPUID instruction,irrespective of the feature set variances across product generations, skus, or segments.

In the case of 1GB support, it is supported in Intel Xeon 5600 series, and in E7 Series. I would expect 1GB page will be supported in the next generation Xeon product built from the Sandy Bridge microarchitecture that serve the same market segment as 5600 series do.

The Xeon 5600 series and E7 seriesare built from the Westmere microarchitecture. Not allproduct skus built from the Westmere microarchitecture supported 1GB page.

Thanks a lot,Shih.
I also expect 1GB page will be supported in the next generation Xeon.

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