I'm trying to narrow down some odd behavior. I configured our hypervisor to catch 0xb faults for disabled interrupts. Then enable the interrupt, but mark the EPT page the IDT vector points at as unreadable. I resume execution which clears the interrupt stack and then throws an ept violation. I then flip the state disabling the interrupt i'm trying and finally re-enable the ept page of the vector and resume execution. Everything works well in bochs.
However, when I go to test on our Nehalem processor it loops through the hypervisor randomly multiple times, successfully! Sometimes it loops through just once, as it should, other times it runs the code 10-12 times. Unfortunately each loop through increments a counter skewing our results. It appears as if the instruction has been cached in some way and doesn't use the current version in memory until an update several into the cache. I am wondering if I have mis-configured the cache and it's running off an old version of memory. I've tried to issue and WBINVD, CPUID, read CR3, and disabled caching of the EPT pages and structures. Have i missed something?
To put the question specifically: what operations do I have to do to invalidate cached mappings (that I might have missed above) to clear the cache when the hypervisor modifies a guest's memory via its ept pages?