On a Sandy Bridge processor I'm trying to find an answer for what the difference is between the following two events. This is based on the information in the developer manual volume 3b part 2 insections 19.1 and 19.3.
- The architecural performance event "LLC Misses" which is also called LONGEST_LAT_CACHE.MISS Event Num: 0x2E Umask Value: 0x41
- MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS Event Num: 0xD4 Umask Value: 0x02
I have seen one post that stated the LLC Misses counts LLC misses due to loads and stores, but not LLC misses due to hardware prefetches.
Could someone help explain the difference between these two events?