Question about pmc event docs for Haswell

Question about pmc event docs for Haswell

In reading vol 3b (253669-047US June 2013), page 19-9, table 19-2 it appears that:

D0/01 references non-existent D0/20
D0/10, D0/40, D0/80 references non-existent D0/02

Are D0/02 and/or D0/20 missing or are the references incorrect?


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    I don't work with Intel but I just measured this stat in a test with locks.. and I'm getting counts for the lock counts on LDs and STs, for "lock cmpxchg" which is atomic and a load and store.  So looks good to me.  Also I've verified that the L2 TLB miss counts work and the split line counts work (which means a request spanned a cacheline).  So even though they are not specified in the SysProg guide.. they're working in HW.  I wish documentation was better handled for their products and assistance was more forthright in their PMCs.  BTW.. PMC 0xD1 doesn't work for LFB counts.  



many thanks for your response. I'm just getting into the PMC realm and I have figured that it will take some time so assistance is needed and appreciated. As you may have seen, I'm trying to characterize the overheads of TSX. I'm planning to analyze both RTM and HLE, but I have so far focused on HLE. My use cases are internal so I will need to code separate test cases whenever I will need to share code to get a second opinion..

Have you looked at TSX yet?


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