My system has got two sockets with Sandy Bridge Processors. Total RAM is 64 GB and has got NUMA enabled.
I am studying two PCI Registers namely, DRAM Rule Register ( for determining interleaving at socket level); and a TAD Register.
for understanding the address mapping scheme in MC.
My question is although there is no interleaving across sockets/numa nodes i.e each NUMA node
has got 32GB( contiguous with no interleaving as per the DRAM Rule Registers). But still each numa node
has got two TAD entries. Documents say that TAD entries correspond to SAD interleaving schemes. Can anyone
help me explain the existence of such TAD entries in this case even though there''s no SAD interleaving. Is it possible ?