I am using an intel xeon machine with id Family 6 and model 45(2D). Is there some way to distinguish between partial and complete data line reads?
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Order Number 325384-047US, June 2013, Vol 3b, page 18-42 lists that in offcore event monitoring, if 0th bit of offcore response MSR (corresponding to address 0x1A6) is turned on, then, counter counts all requests topartial and completecache lines.
Is this the case for all other ways to measure cache misses too? Example LLC references, LLC misses table 19.1 same document.
Currently for measuring no of bytes fetched I am doing something like
Total no of bytes fetched by L3 cache = CR * block size
where CR is the value of counter 3 using offcore monitoring, setting request type to DMND_DATA_RD + PF_LLC_DATA_RD and response type to Any and Snoop to SNP_NONE.