Voltage levels at different frequency levels on Sandy bridge processor

Voltage levels at different frequency levels on Sandy bridge processor

I'm trying to gather some data from the MSR registers about the voltage levels at various frequency levels. I see that the MSR register: IA32_PERF_STATUS output both the current frequency and operating voltage. But the last two hexadecimal bits give the Voltage ID.

sudo modprobe msr
sudo rdmsr -d --bitfield 15:0 0x198

On one of the forums, I see that for Core2Duo you need to substitute in the following linear equation to obtain the Votlage level at a given Frequency level.
0.7125V + VID*0.0125V
and I'm using a Sandy bridge processor. Could you please direct me to a place where I can find the linear equation or help me build it.

Any help will be appreciated.

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Plus, When I read the MSR register - the last 2 bits are always 0. Why would that case occur?

My grub looks like this:

GRUB_CMDLINE_LINUX_DEFAULT="quiet splash intel_pstate=disable"

Look in the System Programming guide provided by Intel.  


It says in table 35-11:

MSR_PERF_STATUS[47:32] * (float) 1/(2^13). (typo in my version says bits [37:32] but I am sure it's [47:32].


Did you consult "Software Development Manuals"?


Yes, I did consult the SDM. I did not find them. Any help will be appreciated.

Yes, I did look at the SDM's. The SDMs provide us with the MSR registers, the bits that represent voltage and the corresponding voltage for the 2 least significant bits.

However, On my sandy bridge processor the last two bits are always zero. Is there anyway out of it?

It seems that lower word of IA32_PERF_STATUS is controlling Intel Speed Step technology,but exact description is not given.


Ok. But do you see any place where the voltage levels at a given frequency level are given?
I don't think they are available in the SDM.
The Table 35-12. MSRs Supported by Intel® Processors based on Intel® microarchitecture code name Sandy Bridge (Contd.) in

Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C
Gives some information..

Yes I would like to see the exact description,but it is not available in SDM (table 35-12).It is interesting what lowest byte is supposed to set?

It'd be great if one of the intel personal sheds some light. since we are not able to figure it out.
The table 35-12 only tells us about the MSR registers and which bits to access for frequency and voltage levels.

Usually if the description is absent the exact info is given as a NDA.


Thank you for that. I figured that as well from the SDM. But how are you sure about the bit changes from 37 to 47?

And, Which bits represent the voltage? which ones represent the frequency? it is 4 digit hexadecimal value.

Moreover, does it represent the VDD or the VCC?

The table 7-1 ends at 1.52V for VCC.

How did you set global_ctrl and event_select?


I'm not trying to set the values. I'm just trying to read them.

To set the values you need to do wrmsr <hex value> <new hex value>

>>>The table 7-1 ends at 1.52V for VCC.>>>

Can you tell me where in SDM I can find this table?


Hello Rajiv,

As perfwise pointed out, the voltage ID for sandbridge is bits 32-47 of MSR IA32_PERF_STATUS (sometimes called MSR_PERF_STATUS).

And perfwise's formula (voltage = VID/(2^13) = VID/8192) is also correct. This is documented in one of the sandybridge specification update docs page 25: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf

However, the spec update also lists an erratum (HSD31) for the reported voltage id where it can be half of the expected value. The erratum says there may be a workaround in the bios and it says that the C-0 stepping of the processors for this spec update are affected. Unfortunately, the doc doesn't say which stepping number corresponds to stepping C-0. So I can't tell if you a hitting the erratum nor if there is a workaround in your bios.

I think you asked if the VID pertains to VCC. Yes. This is stated in the desktop data sheet vol 1 page 89. See the datasheets at http://www.intel.com/content/www/us/en/processors/core/CoreTechnicalResources.html .

I find the docs for a particular processor by going to ark.intel.com, select 'products by code name' at the left, lookup sandybridge, find your specific processor in the list, then click 'download datasheet' on the right. You may get a list of datasheets.... and you have to pick the right one.

Or you can just just google something like 'intel i5-2540m' and click on the ark.intel.com link.

Hope this helps.


Also, you might try looking into the linux kernel source code or the power-governor (cpu-freq?) source code.

I assume they have to deal with voltage id and that source might indicate how to decode values or workaround difficulties.



Thank you.

Hi Pat,

Thank you for your reply. But what is the unit of power there? mV or V or MV?
One more issue is that the voltage doesn't stay constant.. it varies based on the stress on different components of the processor. I thought it is constant irrespective of the stress for a given frequency level, isn't it?

Hope you can clear this one doubt.


Maybe you are seeing fluctuation of the voltage.

Sure. So, I did some calculations... here are the results and I'm sure it is in V. The values presented below is the avg voltage levels when all 4 cores are turned on with user controlled frequency levels.


The question arises if the fluctuation values are related to overall load of CPU(CPU resources) per some unit time as function of aferomentioned load or it is simply voltage fluctuation.I am thinking about  performing some test which hopefully can show some pattern of valtage fluctuation as a function of load. 

You can for example rise your thread priority to real time(Windows terminology) and set its affinity to specific core and perform some intensive calculation and look at voltage values.

I ran some stress microbenchmark (with no cache access) and I see that the voltage is almost constant. "almost" is definitely not a scientific word, but the average error is <1% with a very low SD.

It seems that this could be dynamic voltage scaling and what you are seeing is the scaling step.

Sure. I got that part of it.

Hello Rajiv,

I haven't tried to track voltage but I've always assumed it would vary somewhat with frequency and probably by which cstate the cpu is in.

Some chips let you control the frequency absolutely but others, when the chip is idle, will go into halted states and this probably changes the voltage. You would probably have to switch to using a 'no halting when idle' OS option (on linux you can use the 'idle=poll' boot cmdline option) and keep the cpus fully busy to avoid seeing the voltage change.

Here is a paper which looks interesting but I haven't read it carefully to see how relevant it is. http://people.cs.pitt.edu/~kirk/cs3150spring2010/Multiple_Clock_and_Voltage_Domains_for_Chip_Mu.pdf


Interesting paper.It seems that performance of cpu intensive  applications scales lineary as frequency increases.

Sure, I disabled C-states from the grub and recorded the voltage levels again. I got the results as expected, that is, the values don't fluctuate since the static power doesn't dominate anymore.
It is not exactly linear, it depends on many things like stall-cycles, IO interrupts, kernal thread interrupts, etc

P.S: I worked with Kirk at Pittsburgh earlier this year :)

Hi Rajiv

I commented on results of test performed by the authors of the paper mentioned by Pat.I suppose that exact shape of such a function (voltage fluctuation) will not be linear and in best case it will like sum of many sinusoids.

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