i try to use the perf commands on an Xeon E5 family processor (2620) in order to get cache miss ratio for L2 and L3. I have tried the perf stat commands and read the Inter software developer manual , but i still an confused regarding 3 issues:
-how do i use the unmask value with the event number in order to get the events? the format of the perf stat operans is -rNNN so we need the hex digits, how are they produced from event number and mask?
-which events must i use in order to get L2 misses? the description on the events is a bit confusing....
-for Xeon case where there is L3 , are the LLC misses= L3 misses= total cache misses ( as measured in perf stat)?
any advice would be highly appreciated