Cycles spent requests to DRAM on Ivy/Sandy Bridge

Cycles spent requests to DRAM on Ivy/Sandy Bridge


I was wondering if anyone could point me to the proper hardware counters (and equation) for measuring the fraction of cycles spent servicing memory requests (loads/stores) to DRAM on Ivybridge/Sandybridge?

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It depends on what you mean by "cycles servicing memory requests to DRAM"....

For the Xeon E5-2600 and Xeon E5-2600 v2 processors, you can read the memory controller DRAM CAS counters to determine the exact number of memory reads and writes that went to the DRAMs.  Each transaction takes four DRAM (major) cycles, so you can easily compare the amount of time that the DRAM is busy with data transfers against the elapsed wall clock time.

"Dr. Bandwidth"

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