I'm new to performance monitoring and I want to make sure I understand everything that goes into calculating the L2 hit ratio.
In the source code for the Intel PCM software, the L2 hit ratio is calculated as follows:
uint64 hits = L2Hit; uint64 all = L2Hit + L2HitM + L3UnsharedHit + L3Miss; if (all) return double(hits) / double(all);
The variable name L3UnsharedHit seems to imply that there's something else called an L3SharedHit, which would presumably happen when a load request misses in the L2 but is present in a separate socket's L3 cache. Is there such a thing? Do modern processors with QPI derive any benefit from finding a cache line in another socket's L3, versus having to go out to memory?
Also, I assume the variable L2HitM means the number of misses in the L2, but that doesn't make sense with the variable's name. I haven't been able to track down exactly what event number and umask that corresponds to in the PMU. Is there a better interpretation?
Thanks for your time,