i'm looking at performance variations of my application under a range of power caps. With a low power cap, the perfromance is very bad. With a high power cap, the performance is reasonable. Since RAPL controls the power consumption, it's not so intuitive to construct a mathematic model of power consumption and performance, as using DVFS.
My questions is how RAPL caps the power. (Someone told me, if the power cap is high, it does DVFS. If the power limitation is low, it manipulates clock duty cycles. Is that correct? Where can i find official information?)