Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic Using RAPL to read PP0 and DRAM energy on haswell
by Sameer A.
Tue, 04/05/2016 - 15:47 10
by McCalpin, John
Mon, 04/10/2017 - 14:21
Normal topic Intel DDU and MDT 2013
by Krzysztof T.
Mon, 04/10/2017 - 07:39 0
by Krzysztof T.
Mon, 04/10/2017 - 07:39
Normal topic RAPL power capping: how does it work
by Bo W.
Fri, 04/07/2017 - 06:53 2
by Bo W.
Mon, 04/10/2017 - 06:04
Normal topic how to use rdmsr from my C program?
by anthony b.
Wed, 05/11/2016 - 03:41 3
by Black.S
Thu, 04/06/2017 - 10:08
Normal topic Disable onboard graphics to save power?
by Charlie H.
Mon, 04/03/2017 - 13:12 0
by Charlie H.
Mon, 04/03/2017 - 13:12
Normal topic macOS .kext signing for performance counters
by Aaron H.
Thu, 11/24/2016 - 10:20 2
by Chris S.
Fri, 03/31/2017 - 21:03
Normal topic pcm-memory.x fails to read memory stats
by Somnath M.
Mon, 03/27/2017 - 15:54 1
by Somnath M.
Thu, 03/30/2017 - 18:09
Normal topic Compiling with O3 giving segmentation fault
by Ashutosh L.
Wed, 03/29/2017 - 23:38 0
by Ashutosh L.
Wed, 03/29/2017 - 23:38
Normal topic Are UD2 and INT3 roughly equivalent for stopping speculation
by Chris S.
Wed, 03/29/2017 - 13:11 0
by Chris S.
Wed, 03/29/2017 - 13:11
Normal topic The performance counter can't generate the overflow interrupt
by hiratz s.
Wed, 03/29/2017 - 11:40 0
by hiratz s.
Wed, 03/29/2017 - 11:40
Normal topic Weird Derived Cache Latency
by Min X.
Mon, 03/27/2017 - 20:15 1
by Thomas Willhalm...
Tue, 03/28/2017 - 02:16
Normal topic CPU supports clwb and clflushopt
by kai w.
Mon, 02/13/2017 - 00:45 3
by Thomas Willhalm...
Fri, 03/24/2017 - 06:17
Normal topic Getting a constant frequency on a core
by NC s.
Wed, 03/22/2017 - 07:34 1
by McCalpin, John
Wed, 03/22/2017 - 08:20
Normal topic Intel PCM v2.9 - getting a list of supporting events
by James M.
Thu, 01/21/2016 - 10:53 6
by Patrick Lu (Intel)
Tue, 03/21/2017 - 15:04
Normal topic How to use MTRR on machines with Skylake processors?
by Xinran W.
Thu, 03/16/2017 - 18:42 1
by McCalpin, John
Mon, 03/20/2017 - 08:14
Normal topic How to debug ProcHot?
by Adrian C.
Fri, 03/10/2017 - 21:55 4
by Roman Dementiev...
Fri, 03/17/2017 - 02:42
Hot topic Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?
by Stephen
Fri, 10/03/2014 - 11:29 18
by Steve G.
Mon, 03/13/2017 - 10:25
Normal topic Measuring FLOPS on intel i7 Skylake CPU using PCM
by Huda I.
Wed, 03/08/2017 - 08:48 6
by Roman Dementiev...
Fri, 03/10/2017 - 00:16
Normal topic DEMAND_CODE_RD PMC
by Min X.
Wed, 03/01/2017 - 14:35 7
by McCalpin, John
Mon, 03/06/2017 - 09:05
Normal topic CPU Frequency Changing for Intel CPU
by Kevin
Tue, 02/28/2017 - 12:19 2
by Kevin
Tue, 02/28/2017 - 15:14
Normal topic Sustained 2r1w/cycle GPR code on Skylake architecture
by Jens N.
Tue, 02/28/2017 - 09:35 0
by Jens N.
Tue, 02/28/2017 - 09:35
Normal topic How to control the four hardware prefetchers in L1 and L2 more flexibly?
by hiratz s.
Fri, 02/24/2017 - 14:24 6
by McCalpin, John
Tue, 02/28/2017 - 08:50
Normal topic Ivy Bridge LLC miss
by Min X.
Thu, 02/23/2017 - 23:36 4
by McCalpin, John
Mon, 02/27/2017 - 09:33
Normal topic Why I can not get the Cbox0 PMU in this way?(with code in it)
by Duan Z.
Thu, 02/23/2017 - 00:47 7
by Thomas R.
Mon, 02/27/2017 - 05:17
Normal topic Counting number of uops
by Ayaz A.
Wed, 02/22/2017 - 10:19 3
by McCalpin, John
Fri, 02/24/2017 - 08:51
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Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.