Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
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Topic / Topic starter Post date Replies Last Postsort ascending
Normal topic How to debug ProcHot?
by Adrian C.
Fri, 03/10/2017 - 21:55 4
by Roman Dementiev...
Fri, 03/17/2017 - 02:42
Hot topic Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?
by Stephen
Fri, 10/03/2014 - 11:29 18
by Steve G.
Mon, 03/13/2017 - 10:25
Normal topic Measuring FLOPS on intel i7 Skylake CPU using PCM
by Huda I.
Wed, 03/08/2017 - 08:48 6
by Roman Dementiev...
Fri, 03/10/2017 - 00:16
Normal topic DEMAND_CODE_RD PMC
by Min X.
Wed, 03/01/2017 - 14:35 7
by McCalpin, John
Mon, 03/06/2017 - 09:05
Normal topic CPU Frequency Changing for Intel CPU
by Kevin
Tue, 02/28/2017 - 12:19 2
by Kevin
Tue, 02/28/2017 - 15:14
Normal topic Sustained 2r1w/cycle GPR code on Skylake architecture
by Jens N.
Tue, 02/28/2017 - 09:35 0
by Jens N.
Tue, 02/28/2017 - 09:35
Normal topic How to control the four hardware prefetchers in L1 and L2 more flexibly?
by hiratz s.
Fri, 02/24/2017 - 14:24 6
by McCalpin, John
Tue, 02/28/2017 - 08:50
Normal topic Ivy Bridge LLC miss
by Min X.
Thu, 02/23/2017 - 23:36 4
by McCalpin, John
Mon, 02/27/2017 - 09:33
Normal topic Why I can not get the Cbox0 PMU in this way?(with code in it)
by Duan Z.
Thu, 02/23/2017 - 00:47 7
by Thomas R.
Mon, 02/27/2017 - 05:17
Normal topic Counting number of uops
by Ayaz A.
Wed, 02/22/2017 - 10:19 3
by McCalpin, John
Fri, 02/24/2017 - 08:51
Normal topic Performance event "Pin control (bit 19)"
by JJ
Wed, 02/22/2017 - 07:27 1
by McCalpin, John
Thu, 02/23/2017 - 11:12
Hot topic The accuracy of the performance counter statisitics
by Xin X.
Wed, 08/07/2013 - 07:22 26
by McCalpin, John
Thu, 02/23/2017 - 11:04
Normal topic non-snoop read and non-snoop write. meaning?
by Alexander Alexeev
Tue, 07/16/2013 - 01:53 11
by McCalpin, John
Thu, 02/23/2017 - 08:37
Hot topic How to read performance counters by rdpmc instruction?
by Sergey Shalnov ...
Wed, 10/07/2015 - 22:01 27
by McCalpin, John
Thu, 02/23/2017 - 08:23
Normal topic How to measure remote read or write request of a core using PMU?
by Duan Z.
Mon, 02/20/2017 - 17:54 3
by Duan Z.
Wed, 02/22/2017 - 01:34
Normal topic Does msync come with a cache flushing operation
by kai w.
Fri, 02/17/2017 - 15:52 0
by kai w.
Fri, 02/17/2017 - 15:52
Normal topic DDR2 & DDR3 timings similarities
by CyrIng
Wed, 02/15/2017 - 07:51 5
by CyrIng
Fri, 02/17/2017 - 10:43
Normal topic event to count access memory and PAPI
by Abdo L.
Thu, 02/16/2017 - 13:39 0
by Abdo L.
Thu, 02/16/2017 - 13:39
Normal topic Write Combining Buffer Out of Order Writes and PCIe
by bmeardon
Tue, 02/07/2017 - 11:52 9
by bmeardon
Mon, 02/13/2017 - 09:22
Normal topic My summary of clflush and clflushopt.
by Steven H.
Sun, 02/12/2017 - 13:28 1
by McCalpin, John
Mon, 02/13/2017 - 09:07
Normal topic Measure uncore frequency on my Skylake CPU
by Travis D.
Wed, 02/01/2017 - 14:10 2
by Thomas R.
Mon, 02/13/2017 - 05:23
Normal topic Configure and read iMC Performance Counters with Haswell E5 and missing /sys/devices/ export
by Stephan W.
Thu, 01/19/2017 - 11:00 5
by McCalpin, John
Thu, 02/09/2017 - 09:46
Normal topic Concurrency support of CLFLUSH
by Steven H.
Mon, 02/06/2017 - 15:30 1
by McCalpin, John
Tue, 02/07/2017 - 13:24
Normal topic Effect of DVFS on memory load latency information using PEBS on Haswell
by sridutt
Thu, 02/02/2017 - 20:14 3
by McCalpin, John
Mon, 02/06/2017 - 14:24
Normal topic Disabling turbo boost for only some cores on a socket
by Travis D.
Tue, 01/31/2017 - 14:00 4
by Travis D.
Fri, 02/03/2017 - 12:17
New posts
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Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.