Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic Evaluating dfferent software prefetch schemes SandyBridge and later processors
by andy-nisbet
Wed, 07/25/2012 - 10:13 3
by McCalpin, John
Tue, 09/25/2012 - 15:53
Normal topic DTLB miss counting discrepancy (?)
by arkaprava.basu
Tue, 07/30/2013 - 23:35 5
by perfwise
Thu, 08/01/2013 - 15:25
Normal topic Intel PCM - Can not access CPUs Model Specific Registers MSR
by Mahieddine D.
Wed, 05/28/2014 - 08:52 7
by Patrick Fay (Intel)
Thu, 05/28/2015 - 06:19
Normal topic Little Bug about IntelPerformanceCounterMonitorV2.8/intelpcm.so/Makefile
by wayne z.
Fri, 05/08/2015 - 05:23 1
by Roman Dementiev...
Tue, 05/19/2015 - 00:42
Normal topic Sandy Bridge i5-2500k uncore ARB events
by Ying Y.
Tue, 03/08/2016 - 08:58 3
by A T. (Intel)
Mon, 03/21/2016 - 09:27
Normal topic Does the PDE_CACHE_MISS performance counter count misses in the PDPTE & PML4 cache as well?
by Chang Hyun P.
Sun, 05/29/2016 - 20:00 3
by McCalpin, John
Wed, 06/01/2016 - 15:09
Normal topic Calculating memory stalls in second level cache
by Papote J.
Sun, 05/07/2017 - 13:25 0
by Papote J.
Sun, 05/07/2017 - 13:25
Normal topic Intel Performance Counter Monitor now supports Intel Xeon E7 series and 2nd generation Intel CoreTM processor family
by Thomas Willhalm...
Fri, 07/15/2011 - 08:26 0
by Thomas Willhalm...
Fri, 07/15/2011 - 08:26
Normal topic Questions about Vtune time-sampling when interrupts are disabled.
by Guillermo Navarro
Wed, 08/01/2012 - 00:23 1
by Gary Carleton (...
Fri, 08/03/2012 - 16:27
Normal topic High impact of rdtsc
by Mark D.
Mon, 09/26/2016 - 09:17 5
by McCalpin, John
Thu, 09/29/2016 - 09:15
Normal topic Can not enable the "branch trace store" on SandyBridge
by yakovxu
Wed, 01/04/2012 - 05:35 5
by Patrick Fay (Intel)
Wed, 01/04/2012 - 08:43
Hot topic Sandy bridge performance degradation compare to Westmere
by amk21
Thu, 11/01/2012 - 04:05 42
by amk21
Wed, 11/28/2012 - 12:29
Normal topic Power implications of disabling USB
by Thomas Willhalm...
Mon, 08/26/2013 - 11:20 1
by Patrick Fay (Intel)
Mon, 08/26/2013 - 12:17
Normal topic Can clflush evict any address
by Younis A.
Mon, 09/15/2014 - 13:39 2
by Younis A.
Wed, 09/17/2014 - 00:17
Normal topic intel xeon hardware cache events not supported
by Jacob K.
Sat, 07/25/2015 - 03:55 1
by McCalpin, John
Mon, 07/27/2015 - 13:41
Normal topic PEBS for Haswell architecture
by kai w.
Mon, 11/28/2016 - 22:52 2
by Thomas Willhalm...
Fri, 12/02/2016 - 08:40
Normal topic Intel PCM - errors while using PCM.exe
by pranith
Tue, 04/03/2012 - 08:08 13
by Patrick Fay (Intel)
Tue, 09/10/2013 - 09:01
Normal topic Intel Performance Counter Monitor (Intel PCM) 2.4 released
by Thomas Willhalm...
Tue, 03/26/2013 - 06:05 11
by Roman Dementiev...
Thu, 10/22/2015 - 03:43
Normal topic [BUG][AVX] Invalid code generation using _mm256_unpacklo_pd and _mm256_permute2f128_pd
This topic has been moved to "Intel® C++ Compiler" (View topic)
Normal topic Per core energy analysis
by ARNAB R.
Sat, 12/20/2014 - 23:49 2
by iliyapolak
Tue, 12/23/2014 - 10:37
Normal topic How is transmitted data assigned to a process by the ring bus system of Intel Sandy Bridge
by Steven P.
Mon, 10/12/2015 - 17:38 1
by McCalpin, John
Tue, 10/13/2015 - 12:56
Normal topic Package C-state Residency Counters
by CyrIng
Tue, 02/21/2017 - 09:51 1
by CyrIng
Mon, 02/27/2017 - 08:02
Normal topic Static power consumption increase with T state
by gokussj9
Mon, 06/18/2012 - 08:49 1
by Hussam Mousa (Intel)
Thu, 06/28/2012 - 16:31
Normal topic Shared L1 data cache
by Divino C.
Sat, 06/08/2013 - 14:41 6
by Sergey Kostrov
Sun, 06/09/2013 - 21:32
Normal topic 32 byte store to load forwarding on Sandy Bridge
by Marcin K.
Wed, 03/05/2014 - 00:57 5
by iliyapolak
Tue, 03/11/2014 - 02:35
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Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.