Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Postsort descending
Normal topic Intel ATOM SSE3_ATOM optimization under Windows 32-bit -O3
by Filip Rydlo
Wed, 11/09/2011 - 07:19 4
by Sergey Kostrov
Wed, 11/09/2011 - 07:19
Normal topic Package Power of Intel SB
by Fabian Oboril
Sun, 11/13/2011 - 04:30 2
by Patrick Fay (Intel)
Fri, 11/18/2011 - 06:07
Normal topic Performance measurement on Intel Processors
by pratheekp
Wed, 11/23/2011 - 05:29 3
by OKohl
Wed, 11/23/2011 - 05:29
Normal topic Help me out..
by israfeal
Sat, 11/26/2011 - 09:17 5
by Patrick Fay (Intel)
Sat, 11/26/2011 - 09:17
Normal topic Loop Versioning in Intel compiler
by zakaria-bendifallah
Fri, 07/22/2011 - 10:11 2
by Sergey Kostrov
Mon, 11/28/2011 - 21:07
Normal topic Avoid cache writing on read?
by yotamhc
Tue, 11/29/2011 - 05:36 7
by Sergey Kostrov
Tue, 11/29/2011 - 05:36
Normal topic inline asm vs intrinsics
by roger-evrard
Sat, 11/19/2011 - 05:55 11
by Sergey Kostrov
Thu, 12/01/2011 - 18:21
Normal topic L1 Data Cache in Sandy Bridge
by david42
Mon, 12/05/2011 - 19:14 4
by Patrick Fay (Intel)
Mon, 12/05/2011 - 19:14
Normal topic What are LLC hardware prefetches?
by perfwise
Wed, 12/07/2011 - 12:31 2
by Patrick Fay (Intel)
Wed, 12/07/2011 - 12:31
Normal topic [Sandy-bridge loop buffer]
by zakaria-bendifallah
Fri, 12/16/2011 - 02:03 4
by Tim P.
Mon, 12/19/2011 - 04:21
Normal topic Trying to make sense of L1D (0x51), L2_RQSTS(0x24) and OFFCORE_REQUESTS (0xB0)
by perfwise
Tue, 12/06/2011 - 19:35 2
by Patrick Fay (Intel)
Tue, 12/20/2011 - 08:07
Normal topic Access to Intel(r) Performance Counter Monitor has denied
by Ilan
Wed, 12/14/2011 - 22:47 11
by Roman Dementiev...
Thu, 12/22/2011 - 03:48
Normal topic Passing some memory boundary values to 'prefetcht*' instructions
by Sergey Kostrov
Fri, 12/23/2011 - 06:04 6
by k_sarnath
Fri, 12/23/2011 - 06:04
Normal topic Return Program Counter
by gokussj9
Fri, 12/23/2011 - 06:31 2
by Thomas Willhalm...
Fri, 12/23/2011 - 06:31
Normal topic Performance lost due to context switching by kernel
by Vishal Sharma
Sun, 11/27/2011 - 10:28 1
by Patrick Fay (Intel)
Fri, 12/23/2011 - 19:48
Normal topic Setting MSR 0x1AD (turbo ratio limits) has no effect on Sandy Bridge
by khenglish
Tue, 09/06/2011 - 09:32 4
by terabytes
Sun, 01/01/2012 - 23:40
Normal topic SNB Energy measurements
by terabytes
Mon, 01/02/2012 - 00:42 5
by Patrick Fay (Intel)
Mon, 01/02/2012 - 20:17
Normal topic Can not enable the "branch trace store" on SandyBridge
by yakovxu
Wed, 01/04/2012 - 05:35 5
by Patrick Fay (Intel)
Wed, 01/04/2012 - 08:43
Normal topic Fortran on Xeon X56xx vs Xeon E56xx
by hornos
Sun, 01/08/2012 - 04:56 2
by Tim P.
Sun, 01/08/2012 - 06:02
Normal topic Intel PCM: FLT_SENT, NULL_IDLE Events?
by tim.kiefer
Mon, 01/09/2012 - 05:28 5
by tim.kiefer
Fri, 01/13/2012 - 03:39
Normal topic About i7 2700k and RAM help.
by nikromants
Fri, 01/13/2012 - 16:22 1
by Patrick Fay (Intel)
Fri, 01/13/2012 - 18:21
Normal topic Documentation on clock cycles for various Sandy Bridge instructions?
by christian.conve...
Wed, 01/18/2012 - 14:12 1
by Patrick Fay (Intel)
Wed, 01/18/2012 - 17:39
Normal topic HOW to get the L1,L2 Cache Miss of an intel i5 Sandy Bridge
by eandy
Thu, 01/26/2012 - 11:21 2
by Shannon Cepeda ...
Thu, 01/26/2012 - 11:30
Normal topic [PCM] L2/L3 Cache Miss Values Are Alway Zero on Sandy Bridge
by mikeb01
Fri, 01/27/2012 - 00:36 3
by Roman Dementiev...
Fri, 01/27/2012 - 01:26
Normal topic How to apply 'developer system programming manual' on SNB
by GHui
Wed, 02/01/2012 - 00:01 10
by Patrick Fay (Intel)
Wed, 02/01/2012 - 00:01
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For more complete information about compiler optimizations, see our Optimization Notice.