Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

Announcements
 
Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Topic / Topic starter Post date Replies Last Post
Normal topic Intel® 5 Series HM55 chipset Power-Up questions
by Lior M.
Thu, 10/02/2014 - 00:42 2
by Lior M.
Sun, 10/05/2014 - 01:10
Normal topic Using RAPL to read PP0 and DRAM energy on haswell
by Sameer A.
Tue, 04/05/2016 - 15:47 10
by McCalpin, John
Mon, 04/10/2017 - 14:21
Normal topic DDR2 & DDR3 timings similarities
by CyrIng
Wed, 02/15/2017 - 07:51 5
by CyrIng
Fri, 02/17/2017 - 10:43
Normal topic Problem with Multiple display monitoring on DELL XPS 14 Z
by ahmedmagd
Sun, 07/15/2012 - 02:03 3
by Hussam Mousa (Intel)
Tue, 07/17/2012 - 10:46
Normal topic Where I can get docs for CPUID and CPUID-like assembly registers ?
by bp
Thu, 07/25/2013 - 01:18 11
by iliyapolak
Fri, 07/26/2013 - 03:14
Normal topic Overwrite Locked Bits in a Memory Controller
by Saptarshi S.
Mon, 11/18/2013 - 16:34 2
by Patrick Fay (Intel)
Fri, 01/24/2014 - 07:53
Normal topic Problem in aligning Fortran arrays in simple code example
by CK
Tue, 01/27/2015 - 05:55 4
by CK
Wed, 01/28/2015 - 06:09
Normal topic Breaking down data access by cache and memory levels
by Jee C.
Fri, 03/28/2014 - 10:15 1
by McCalpin, John
Tue, 04/01/2014 - 15:57
Normal topic Question about Core Specificity Encoding option for reading cpu performace counters
by Hamid Reza K.
Wed, 04/01/2015 - 10:43 1
by McCalpin, John
Wed, 04/01/2015 - 11:13
Normal topic Sudden change in Haswell power consumption
by futureishere
Tue, 08/04/2015 - 09:06 0
by futureishere
Tue, 08/04/2015 - 09:06
Normal topic Problem while using PCM in Windows server 2012 R2
by zhihong l.
Wed, 06/15/2016 - 18:16 10
by Roman Dementiev...
Wed, 06/29/2016 - 08:24
Normal topic 0 L3 Cache Misses reported
by (name withheld)
Tue, 06/13/2017 - 21:00 2
by Roman Dementiev...
Mon, 06/19/2017 - 04:46
Normal topic Trying to make sense of L1D (0x51), L2_RQSTS(0x24) and OFFCORE_REQUESTS (0xB0)
by perfwise
Tue, 12/06/2011 - 19:35 2
by Patrick Fay (Intel)
Tue, 12/20/2011 - 08:07
Normal topic Performance Monitoring Event tables
by Michael G.
Sat, 10/20/2012 - 14:50 1
by Shih Kuo (Intel)
Mon, 11/12/2012 - 16:27
Normal topic How to profile the communication between Host and Mic during Offload Mode
by 振 徐.
Sun, 11/01/2015 - 17:51 0
by 振 徐.
Sun, 11/01/2015 - 17:51
Normal topic Why QPI traffic captured by PCM is larger than bandwith of QPI port?
by li y.
Mon, 10/10/2016 - 02:34 2
by li y.
Wed, 10/12/2016 - 23:33
Normal topic PCIe transfers vs core-to-core communication
by stardust496
Mon, 03/26/2012 - 03:12 1
by Hussam Mousa (Intel)
Mon, 03/26/2012 - 03:12
Normal topic Memory bound characterization on Ivy Bridge
by Yunqi Z.
Mon, 03/04/2013 - 14:56 7
by perfwise
Wed, 03/06/2013 - 04:45
Hot topic The accuracy of the performance counter statisitics
by Xin X.
Wed, 08/07/2013 - 07:22 26
by McCalpin, John
Thu, 02/23/2017 - 11:04
Normal topic Configuring cache partitioning; how?
by Tim Day
Thu, 07/31/2014 - 10:03 3
by McCalpin, John
Thu, 07/31/2014 - 16:46
Normal topic Power Capping by Power Governor and Power Gadget on Linux
by Kevin
Wed, 02/10/2016 - 08:47 9
by Koji T.
Tue, 06/21/2016 - 12:59
Normal topic Measure memory bandwidth on Broadwell EX
by Harry L.
Fri, 12/09/2016 - 18:14 4
by Roman Dementiev...
Thu, 01/05/2017 - 01:14
Normal topic Ivy Bridge performance monitoring events CYCLE_ACTIVITY.*?
by JimH
Mon, 06/11/2012 - 16:22 5
by Divino C.
Tue, 09/03/2013 - 11:11
Normal topic Xeon E5 Family : Integrated Memory Controller
by Saptarshi S.
Wed, 05/29/2013 - 19:12 3
by McCalpin, John
Thu, 05/30/2013 - 08:27
Normal topic Invalid Core Cycle Count
by Samuel M.
Thu, 09/19/2013 - 15:37 4
by Samuel M.
Tue, 10/15/2013 - 13:30
New posts
No new posts
Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.