Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
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Topic / Topic startersort descending Post date Replies Last Post
Normal topic Good block diagram of Ivy Bridge architecture
by dehvidc1
Wed, 05/11/2016 - 00:36 3
by dehvidc1
Thu, 05/12/2016 - 16:47
Normal topic GPU (Intel HD Graphics) hardware counters
by Sankaralingam P.
Thu, 02/18/2016 - 22:42 0
by Sankaralingam P.
Thu, 02/18/2016 - 22:42
Normal topic Graphics and Wireless Components Power Dissipation
by Carlos P.
Sun, 10/11/2015 - 13:36 0
by Carlos P.
Sun, 10/11/2015 - 13:36
Normal topic HA performance events
by Bo W.
Mon, 11/07/2016 - 07:30 4
by Bo W.
Thu, 11/10/2016 - 10:43
Normal topic Handling of IERR
by Babis C.
Sat, 04/02/2016 - 07:37 0
by Babis C.
Sat, 04/02/2016 - 07:37
Normal topic Handling Overflows in Programmable Counters
by Ravitheja G.
Wed, 06/14/2017 - 08:31 2
by Ravitheja G.
Mon, 06/19/2017 - 09:04
Normal topic Hang in /dev/cpu/0/msr
by GHui
Thu, 12/15/2016 - 19:16 3
by McCalpin, John
Tue, 12/20/2016 - 09:48
Normal topic Hardware event construction
by Hanqing H.
Sat, 03/23/2013 - 14:50 6
by iliyapolak
Wed, 03/27/2013 - 00:46
Normal topic Hardware fatal error
by patross2
Wed, 08/08/2012 - 13:40 1
by Thomas Willhalm...
Wed, 08/08/2012 - 20:44
Normal topic Haswell core power sensor, not exist !
by Aljabry, Naif
Wed, 10/05/2016 - 12:59 2
by Aljabry, Naif
Wed, 10/05/2016 - 14:45
Hot topic Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?
by Stephen
Fri, 10/03/2014 - 11:29 18
by Steve G.
Mon, 03/13/2017 - 10:25
Normal topic Haswell loop alignment vs. unrolling
by Tim P.
Wed, 09/09/2015 - 05:49 2
by Tim P.
Wed, 09/16/2015 - 12:08
Normal topic Haswell memory bandwidth
by Tim P.
Sun, 01/01/2017 - 03:08 3
by Thomas Willhalm...
Wed, 01/04/2017 - 04:11
Normal topic Haswell PMU HW doesn't support sampling/overflow-interrupts (LBR)???
by Mark D.
Thu, 05/18/2017 - 10:17 0
by Mark D.
Thu, 05/18/2017 - 10:17
Normal topic Have a beeping problem with new ram memory.
by pinger d.
Sun, 03/30/2014 - 13:19 4
by iliyapolak
Mon, 03/31/2014 - 06:22
Normal topic help for tuning application's startup
by jinjunsheng
Tue, 10/18/2011 - 03:45 5
by iliyapolak
Thu, 02/14/2013 - 22:55
Normal topic Help me out..
by israfeal
Sat, 11/26/2011 - 09:17 5
by Patrick Fay (Intel)
Sat, 11/26/2011 - 09:17
Normal topic High impact of rdtsc
by Mark D.
Mon, 09/26/2016 - 09:17 5
by McCalpin, John
Thu, 09/29/2016 - 09:15
Normal topic High number of retired instructions
by Tomer M.
Tue, 04/12/2016 - 06:45 2
by Tomer M.
Tue, 04/12/2016 - 07:09
Normal topic Higher cache-to-cache and memory latencies on E5-2689 v4 vs E5-2667 v3
by Florian H.
Mon, 10/10/2016 - 05:09 1
by McCalpin, John
Mon, 10/10/2016 - 07:40
Normal topic How 32 bytes alignment affect uop cache?
by Wei M.
Wed, 10/16/2013 - 15:35 6
by iliyapolak
Thu, 10/17/2013 - 10:50
Normal topic How branches in loop body affect the performance when unrolling?
by Peng Z.
Sun, 07/26/2015 - 23:36 3
by Tim P.
Tue, 07/28/2015 - 05:04
Normal topic How can i building Intel PCM without NMI watchdog check?
by Wenqin C.
Fri, 12/11/2015 - 01:43 3
by Wenqin C.
Sun, 12/13/2015 - 03:51
Hot topic How can I compile the MSR driver?
by Antonio v.
Thu, 02/21/2013 - 12:23 25
by iliyapolak
Sun, 03/23/2014 - 04:03
Normal topic How can i scale only one core's frequency in a multi-core processor?(Monitor through PMU)
by Songtao.H
Fri, 07/26/2013 - 04:58 9
by McCalpin, John
Tue, 01/19/2016 - 09:43
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Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.