Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Using Intel PAL (Platform Analysis Library)
by Sankaralingam P.
Fri, 03/11/2016 - 12:00 1
by Ziad S. (Intel)
Mon, 04/18/2016 - 14:47
Normal topic AES-NI instructions statistics
by vlad3
Fri, 08/19/2011 - 01:02 1
by Patrick Fay (Intel)
Fri, 08/19/2011 - 01:02
Normal topic unaligned data access for -xHost option on Intel-AVX platform
by felixdietzsch
Fri, 06/13/2014 - 05:41 1
by Tim P.
Fri, 06/13/2014 - 06:10
Normal topic Interpreting READ / WRITE from PCM
by Kyle Brandt
Wed, 04/11/2012 - 11:51 1
by Patrick Fay (Intel)
Wed, 04/11/2012 - 12:41
Normal topic SANDY BRIDGE ADDRESS MAPPING SCHEME
by Saptarshi S.
Sun, 09/01/2013 - 19:01 1
by Patrick Fay (Intel)
Sun, 09/01/2013 - 19:14
Normal topic Access to Intel(r) Performance Counter Monitor has denied (no MSR or PCI CFG space access).
by Shuja-ur-Rehman B.
Thu, 04/14/2016 - 03:56 1
by Carlos P.
Tue, 05/03/2016 - 12:44
Normal topic Is there an interaction between P-states and C1 state?
by John McCalpin
Wed, 03/19/2014 - 10:31 1
by John McCalpin
Tue, 07/15/2014 - 14:14
Normal topic Internal Energy unit in PCM
by Lu L.
Mon, 12/16/2013 - 01:14 1
by Roman Dementiev...
Mon, 12/16/2013 - 01:16
Normal topic Shared memory on Nehalem
by Madhav A.
Mon, 01/20/2014 - 08:13 1
by Patrick Fay (Intel)
Fri, 01/24/2014 - 06:31
Normal topic about QPI cmd
by Yongbo C.
Thu, 09/01/2016 - 00:37 1
by Thomas Willhalm...
Thu, 09/01/2016 - 02:02
Normal topic Null
by Zara g.
Thu, 09/05/2013 - 04:17 1
by Tim P.
Thu, 09/05/2013 - 05:45
Normal topic RAPL MSR Interface
by Kenan L.
Tue, 10/30/2012 - 10:41 1
by Roman Dementiev...
Tue, 10/30/2012 - 14:36
Normal topic PCM v2.6 hangs
by nir g.
Sun, 08/03/2014 - 04:08 1
by Roman Dementiev...
Sun, 08/03/2014 - 05:54
Normal topic Not PMCx reset working when collecting raw PEBS dump
by jaeyoung j.
Tue, 03/03/2015 - 00:12 1
by Patrick Fay (Intel)
Fri, 03/06/2015 - 08:17
Normal topic About i7 2700k and RAM help.
by nikromants
Fri, 01/13/2012 - 16:22 1
by Patrick Fay (Intel)
Fri, 01/13/2012 - 18:21
Normal topic L1D Latency Breakdown
by Andreas S.
Fri, 04/19/2013 - 05:45 1
by Patrick Fay (Intel)
Fri, 04/19/2013 - 07:03
Normal topic Intel Extreme Memory Profile (XMP) 2.0 Specification
by John S.
Thu, 12/25/2014 - 11:41 1
by Stefanos Konsta...
Wed, 01/07/2015 - 23:43
Normal topic How is transmitted data assigned to a process by the ring bus system of Intel Sandy Bridge
by Steven P.
Mon, 10/12/2015 - 17:38 1
by John McCalpin
Tue, 10/13/2015 - 12:56
Normal topic RDPMC vs. RDMSR and counters for branch predictor
by Minjang.Kim
Thu, 05/03/2012 - 08:29 1
by Roman Dementiev...
Fri, 05/04/2012 - 01:59
Normal topic Power gating Execution units of HD graphics using MSR
by GA I.
Wed, 08/27/2014 - 07:44 1
by Patrick Fay (Intel)
Wed, 09/03/2014 - 08:23
Normal topic how to use rdmsr from my C program?
by anthony b.
Wed, 05/11/2016 - 03:41 1
by Thomas R.
Thu, 05/12/2016 - 01:02
Normal topic What is the signal raised when execution stage detects a misprediction?
by T C
Sat, 03/07/2015 - 10:11 1
by Seth Abraham (Intel)
Fri, 03/27/2015 - 12:36
Normal topic what's the event number of RxR_INT_STARVED.IRQ in E5-2600 CPU
by li d.
Mon, 08/26/2013 - 05:22 1
by Tongliang L.
Tue, 08/27/2013 - 01:52
Normal topic Modifying QPI Routing Table Array.
by wonjun s.
Thu, 05/09/2013 - 11:31 1
by Patrick Fay (Intel)
Thu, 05/09/2013 - 12:54
Normal topic Is it possible to use RAPL interfaces on Xeon E3 1200 (v2, v3) processors?
by jaeyoung j.
Thu, 11/21/2013 - 02:20 1
by Patrick Fay (Intel)
Thu, 11/21/2013 - 07:37
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For more complete information about compiler optimizations, see our Optimization Notice.