Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Topic / Topic starter Post date Replies Last Post
Normal topic retired SIMD instructions in VTUne Amplifer XE 2015
by Chris A.
Fri, 09/12/2014 - 08:06 2
by iliyapolak
Sun, 09/14/2014 - 02:52
Normal topic Intel(R) Memory Latency Checker released
by Thomas Willhalm...
Fri, 12/13/2013 - 00:49 2
by Thomas Willhalm...
Fri, 12/13/2013 - 20:03
Normal topic Is stall cycles all for memory access?
by Shouvik B.
Mon, 10/01/2012 - 17:20 3
by Shouvik B.
Thu, 10/04/2012 - 16:52
Normal topic sys_reset# use with Intel® 5 Series HM55 chipset and an embedded COM Express™ Intel® Core™ i7 Celeron processor
by Lior M.
Sun, 09/28/2014 - 02:26 0
by Lior M.
Sun, 09/28/2014 - 02:26
Normal topic counting flops (SIMD)
by José Luis G.
Fri, 01/10/2014 - 17:15 8
by John D. McCalpin
Wed, 01/15/2014 - 12:48
Normal topic Increasing Stride
by schwald
Mon, 03/26/2012 - 05:45 4
by Patrick Fay (Intel)
Mon, 04/02/2012 - 20:53
Hot topic Strange behaviour of Intel Xeon E3-1220v2
by Tommy F.
Tue, 05/14/2013 - 15:05 31
by iliyapolak
Thu, 05/16/2013 - 22:18
Normal topic Information about PCM PCIe counters
by Anuj K.
Tue, 03/24/2015 - 22:32 3
by Patrick Lu (Intel)
Wed, 03/25/2015 - 09:55
Normal topic How to know the exact cache associative on processor
by zhangyihere
Wed, 08/01/2012 - 05:29 2
by iliyapolak
Sat, 12/22/2012 - 01:06
Normal topic Package Average Bandwidth
by Divino C.
Tue, 07/22/2014 - 11:44 1
by Divino C.
Wed, 07/23/2014 - 08:06
Normal topic Cache Coherence in Ivy Bridge
by Divino C.
Thu, 10/24/2013 - 13:15 10
by iliyapolak
Mon, 10/28/2013 - 00:22
Normal topic [PCM] L2/L3 Cache Miss Values Are Alway Zero on Sandy Bridge
by mikeb01
Fri, 01/27/2012 - 00:36 3
by Roman Dementiev...
Fri, 01/27/2012 - 01:26
Normal topic Asymetrical performance between PCIe peer-to-peer devices
by S G.
Tue, 03/26/2013 - 09:32 0
by S G.
Tue, 03/26/2013 - 09:32
Normal topic RAPL DRAM power limit
by Saeid B.
Tue, 02/17/2015 - 14:07 3
by Patrick Fay (Intel)
Fri, 03/06/2015 - 08:05
Hot topic Intel Memory Latency Checker v2.0 released
by Thomas Willhalm...
Mon, 06/30/2014 - 04:29 24
by Ming C.
Mon, 07/28/2014 - 19:36
Normal topic How to alter the cache write policy while working with Intel X5675 series
by priyanka06
Thu, 06/28/2012 - 12:12 1
by Hussam Mousa (Intel)
Thu, 06/28/2012 - 16:27
Normal topic Sandy Bridge RAPL energy counter overlap?
by John D. McCalpin
Wed, 09/04/2013 - 15:42 0
by John D. McCalpin
Wed, 09/04/2013 - 15:42
Normal topic How Graphics Base Frequency Caluculate
by oniel-kumar (Intel)
Mon, 10/03/2011 - 09:47 1
by Hussam Mousa (Intel)
Mon, 10/03/2011 - 09:47
Normal topic [PCM] Last Level Cache Miss on SNB-Server
by GHui
Fri, 01/04/2013 - 00:48 8
by iliyapolak
Sat, 01/05/2013 - 22:27
Normal topic Why UOPS_RETIRED.ALL greater than UOPS_RETIRED.RETIRE_SLOTS
by Alexander Alexeev
Tue, 11/18/2014 - 08:29 0
by Alexander Alexeev
Tue, 11/18/2014 - 08:29
Normal topic Trouble getting useful information from the PCM
by Kirk S.
Sun, 03/30/2014 - 13:48 1
by Roman Dementiev...
Mon, 03/31/2014 - 00:04
Normal topic 100% usage on Core 1
by orvan
Sun, 05/13/2012 - 07:18 8
by iliyapolak
Fri, 02/15/2013 - 23:23
Normal topic clarification regarding PCM output.
by ran t.
Wed, 07/03/2013 - 23:06 5
by ran t.
Mon, 07/29/2013 - 04:33
Normal topic PCM can not work with suse11 sp1
by Wang Ruifeng
Wed, 08/14/2013 - 01:17 9
by Tongliang L.
Tue, 08/20/2013 - 20:05
Normal topic RAPL interface for Sandy Bridge MSR update rate
by Akshay Venkatesh
Sat, 06/02/2012 - 03:38 1
by Hussam Mousa (Intel)
Thu, 07/12/2012 - 09:41
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Hot topic with new posts
Hot topic without new posts
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For more complete information about compiler optimizations, see our Optimization Notice.